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[209.132.180.131]) by mx.google.com with ESMTPS id xy7si7280163pac.183.2016.11.03.03.16.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Nov 2016 03:16:06 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-return-94306-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of binutils-return-94306-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=binutils-return-94306-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=pSH0s0EyXfqWYUC0lLBf4kBqQ77Zpe/32IzuaLScBeYZwqzLd+o0z XCk2W7rE5ENAYjPxh7xZodZbDpxokJOGMEPx+mBFGDc5mllWY5xAJgitVDNBnXv1 gOXf9f51vJxBTQd4X1EGqgFZnYGVUn8K0ouA7xxTSL2KT6Ps/kgcvo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id :mime-version:content-type:content-transfer-encoding; s=default; bh=KIYgWjCRFChAFCe1cPVaRQ6VLeM=; b=OpYu1OrJhTqWrd0wjveFGFtpssux JTEdCwJNlMt5lH5d1wZvp6++jM6UHKxDN99yhGLIJLtoGWs3vnAPOL8wWiVWQnJj QrzNOeGDyXYVgA+ZtUKJnNUV37YmLDzomiIrUvEGMTr6k8vgJ5MDRv2V0Xj9lK5O cn7GMVmU46P/x14= Received: (qmail 82886 invoked by alias); 3 Nov 2016 10:15:32 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Delivered-To: mailing list binutils@sourceware.org Received: (qmail 82829 invoked by uid 89); 3 Nov 2016 10:15:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=samsung, Samsung, 201611 X-HELO: mail-pf0-f182.google.com Received: from mail-pf0-f182.google.com (HELO mail-pf0-f182.google.com) (209.85.192.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 03 Nov 2016 10:15:21 +0000 Received: by mail-pf0-f182.google.com with SMTP id d2so29642275pfd.0 for ; Thu, 03 Nov 2016 03:15:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Qv6xNgaJaVX+TVZlG7ZS7Zf7BrXjzPWIwjXjOXr1pRU=; b=k5H+5Cs77p1BTIShBHJW29B77iSeu4k5J8rXPytcEN+1YusySxfQry3Vch5lgUmQdn kd+fiUwbXIokN/uUNR3D4aD8jByQbeSCoorag2BtjVEBSxL7ROYjy1cdm3luzgoEezOY P0B3O7eitWlGxq/xsBNTY0t8j+l/L+qt1m865uXBi8c1KdrD1z/NItjPbWDz9HeLJL3l pc1PAtx7WX2eiMUrg161gUrD53Sw4DHIF06odzW330qEQxjoxB6SKVgSTDAdpuxeXy0x I0SBwx2eLcfEuh5b3nIdrj0vAUe4+5SKJMrXkGUz3IKihCW3322CghMWwQNujJmuNDoG dkCw== X-Gm-Message-State: ABUngveWI7zKR1S0ZOTgShE9AmIQ9RGuDrVfP2O+ASUl1FzvqhlcAZeIivglVpQA179sxY3s X-Received: by 10.99.167.67 with SMTP id w3mr12880597pgo.1.1478168119722; Thu, 03 Nov 2016 03:15:19 -0700 (PDT) Received: from linaro-laptop.intra.reserved-bit.com ([124.248.185.144]) by smtp.gmail.com with ESMTPSA id p25sm5152736pfk.20.2016.11.03.03.15.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Nov 2016 03:15:18 -0700 (PDT) From: Siddhesh Poyarekar To: binutils@sourceware.org Cc: jim.wilson@linaro.org, Siddhesh Poyarekar Subject: [PATCH] New option falkor for Qualcomm server part Date: Thu, 3 Nov 2016 15:45:02 +0530 Message-Id: <1478168102-14945-1-git-send-email-siddhesh.poyarekar@linaro.org> MIME-Version: 1.0 This adds an option for the Qualcomm falkor core, the corresponding gcc patch is here: https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00262.html This was tested with aarch64 and armhf builds and make check and also by building and running SPEC2006. Siddhesh gas/ * config/tc-aarch64.c (aarch64_cpus): Add falkor. * config/tc-arm.c (arm_cpus): Likewise. * doc/c-aarch64.texi: Likewise. * doc/c-arm.texi: Likewise. --- gas/config/tc-aarch64.c | 3 +++ gas/config/tc-arm.c | 3 +++ gas/doc/c-aarch64.texi | 1 + gas/doc/c-arm.texi | 1 + 4 files changed, 8 insertions(+) -- 2.7.4 diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 34fdc53..c62be49 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7763,6 +7763,9 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = { {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8, AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), "Samsung Exynos M1"}, + {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8, + AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), + "Qualcomm Falkor"}, {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8, AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), "Qualcomm QDF24XX"}, diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 6482ef9..d8fa58b 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -25391,6 +25391,9 @@ static const struct arm_cpu_option_table arm_cpus[] = ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Samsung " \ "Exynos M1"), + ARM_CPU_OPT ("falkor", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + "Qualcomm " + "Falkor"), ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Qualcomm " "QDF24XX"), diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 6f9f0cc..57937cb 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -61,6 +61,7 @@ on the target processor. The following processor names are recognized: @code{cortex-a72}, @code{cortex-a73}, @code{exynos-m1}, +@code{falkor}, @code{qdf24xx}, @code{thunderx}, @code{vulcan}, diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 0cf7390..8ea6045 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -140,6 +140,7 @@ recognized: @code{exynos-m1}, @code{marvell-pj4}, @code{marvell-whitney}, +@code{falkor}, @code{qdf24xx}, @code{xgene1}, @code{xgene2},