From patchwork Mon Mar 7 16:22:08 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 408 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:42:25 -0000 Delivered-To: patches@linaro.org Received: by 10.224.60.68 with SMTP id o4cs107054qah; Mon, 7 Mar 2011 08:20:19 -0800 (PST) Received: by 10.142.238.10 with SMTP id l10mr3390573wfh.90.1299514818384; Mon, 07 Mar 2011 08:20:18 -0800 (PST) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id y5si7293474wfj.138.2011.03.07.08.20.17 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 07 Mar 2011 08:20:18 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: by pzk5 with SMTP id 5so1110068pzk.37 for ; Mon, 07 Mar 2011 08:20:17 -0800 (PST) Received: by 10.142.7.10 with SMTP id 10mr3333701wfg.390.1299514817481; Mon, 07 Mar 2011 08:20:17 -0800 (PST) Received: from localhost.localdomain ([114.216.147.253]) by mx.google.com with ESMTPS id w11sm4629111wfh.6.2011.03.07.08.20.11 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 07 Mar 2011 08:20:16 -0800 (PST) From: Shawn Guo To: linaro-dev@lists.linaro.org, devicetree-discuss@lists.ozlabs.org Cc: patches@linaro.org, Shawn Guo Subject: [PATCH 1/5] arm/dts: babbage: add gpt and uart related clock nodes Date: Tue, 8 Mar 2011 00:22:08 +0800 Message-Id: <1299514932-13558-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1299514932-13558-1-git-send-email-shawn.guo@linaro.org> References: <1299514932-13558-1-git-send-email-shawn.guo@linaro.org> The patch is to add all gpt, uart related dt clock nodes for babbage. It sticks to the clock name used in clock-mx51-mx53.c, so that everything gets consistent to Reference Manual. For example, the numbering in clock name usually starts from 1, while 'reg' property numbering starts from 0 to easy clock binding. Besides the generally used clock bindings, the following properties are proposed in this patch. * clock-alias Like clock-outputs to reflect cl->dev_id, property clock-alias is defined to reflect cl->con_id. * clock-depend The mxc 'struct clk' has the member 'secondary' to refer to the clock that the 'clk' has dependency on. This 'secondary' clock needs to be on whenever the 'clk' is set to on. This clock-depend property is defined to reflect this 'secondary' clock. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/babbage.dts | 162 +++++++++++++++++++++++++++++++++++++++-- 1 files changed, 156 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/babbage.dts b/arch/arm/boot/dts/babbage.dts index 46a3071..1774cec 100644 --- a/arch/arm/boot/dts/babbage.dts +++ b/arch/arm/boot/dts/babbage.dts @@ -35,19 +35,169 @@ #address-cells = <1>; #size-cells = <0>; - uart0_clk: uart@0 { + ckil_clk: clkil { + compatible = "fixed-clock"; + #frequency-cells = <1>; + clock-outputs = "clil"; + clock-frequency = <32768>; + }; + + ckih_clk: ckih { + compatible = "fixed-clock"; + #frequency-cells = <1>; + clock-outputs = "ckih"; + clock-frequency = <22579200>; + }; + + osc_clk: soc { + compatible = "fixed-clock"; + #frequency-cells = <1>; + clock-outputs = "osc"; + clock-frequency = <24000000>; + }; + + pll1_main_clk: pll1_main { + compatible = "clock"; + reg = <0>; + clock-outputs = "pll1_main"; + clock-source = <&osc_clk>; + }; + + pll1_sw_clk: pll_switch@0 { + compatible = "clock"; + reg = <0>; + clock-outputs = "pll1_sw"; + clock-source = <&pll1_main_clk>; + }; + + pll2_sw_clk: pll_switch@1 { + compatible = "clock"; + reg = <1>; + clock-outputs = "pll2_sw"; + clock-source = <&osc_clk>; + }; + + pll3_sw_clk: pll_switch@2 { + compatible = "clock"; + reg = <2>; + clock-outputs = "pll3_sw"; + clock-source = <&osc_clk>; + }; + + lp_apm_clk: lp_apm { + compatible = "clock"; + clock-outputs = "lp_apm"; + clock-source = <&osc_clk>; + }; + + main_bus_clk: main_bus { + compatible = "clock"; + clock-outputs = "main_bus"; + clock-source = <&pll2_sw_clk>; + }; + + ahb_clk: ahb { + compatible = "clock"; + clock-outputs = "ahb"; + clock-source = <&main_bus_clk>; + }; + + ipg_clk: ipg { + compatible = "clock"; + clock-outputs = "ipg"; + clock-source = <&ahb_clk>; + }; + + spba_clk: spba { + compatible = "clock"; + clock-outputs = "spba"; + clock-source = <&ipg_clk>; + }; + + ahb_max_clk: ahb_max { + compatible = "clock"; + clock-outputs = "ahb_max"; + clock-source = <&ahb_clk>; + }; + + aips_tz1_clk: aips_tz@0 { + compatible = "clock"; + reg = <0>; + clock-outputs = "aips_tz1"; + clock-source = <&ahb_clk>; + clock-depend = <&ahb_max_clk>; + }; + + aips_tz2_clk: aips_tz@1 { + compatible = "clock"; + reg = <1>; + clock-outputs = "aips_tz2"; + clock-source = <&ahb_clk>; + clock-depend = <&ahb_max_clk>; + }; + + gpt_ipg_clk: gpt_ipg { + compatible = "clock"; + clock-outputs = "gpt_ipg"; + clock-source = <&ipg_clk>; + }; + + gpt_clk: gpt { + compatible = "clock"; + clock-outputs = "gpt"; + clock-source = <&ipg_clk>; + clock-depend = <&gpt_ipg_clk>; + }; + + uart1_ipg_clk: uart_ipg@0 { compatible = "clock"; + reg = <0>; + clock-outputs = "uart1_ipg"; + clock-source = <&ipg_clk>; + clock-depend = <&aips_tz1_clk>; + }; + + uart2_ipg_clk: uart_ipg@1 { + compatible = "clock"; + reg = <1>; + clock-outputs = "uart2_ipg"; + clock-source = <&ipg_clk>; + clock-depend = <&aips_tz1_clk>; + }; + + uart3_ipg_clk: uart_ipg@2 { + compatible = "clock"; + reg = <2>; + clock-outputs = "uart3_ipg"; + clock-source = <&ipg_clk>; + clock-depend = <&spba_clk>; + }; + + uart_root_clk: uart_root { + compatible = "clock"; + clock-outputs = "uart_root"; + clock-source = <&pll2_sw_clk>; + }; + + uart1_clk: uart@0 { + compatible = "clock"; + reg = <0>; clock-outputs = "imx-uart.0"; + clock-source = <&uart_root_clk>; }; - uart1_clk: uart@1 { + uart2_clk: uart@1 { compatible = "clock"; + reg = <1>; clock-outputs = "imx-uart.1"; + clock-source = <&uart_root_clk>; }; - uart2_clk: uart@2 { + uart3_clk: uart@2 { compatible = "clock"; + reg = <2>; clock-outputs = "imx-uart.2"; + clock-source = <&uart_root_clk>; }; fec_clk: fec@0 { @@ -67,7 +217,7 @@ reg = <0xc000 0x1000>; interrupts = <0x21>; rts-cts; - uart-clock = <&uart2_clk>, "uart"; + uart-clock = <&uart3_clk>, "uart"; }; }; @@ -82,7 +232,7 @@ reg = <0xbc000 0x1000>; interrupts = <0x1f>; rts-cts; - uart-clock = <&uart0_clk>, "uart"; + uart-clock = <&uart1_clk>, "uart"; }; imx-uart@c0000 { @@ -90,7 +240,7 @@ reg = <0xc0000 0x1000>; interrupts = <0x20>; rts-cts; - uart-clock = <&uart1_clk>, "uart"; + uart-clock = <&uart2_clk>, "uart"; }; };