From patchwork Thu Jan 3 11:59:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 154715 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp576130ljp; Thu, 3 Jan 2019 04:00:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/WXQzElEfWq7mzBLRKlKVUuuHdAvQfyXxn+8vhoJJbfmohvF0CpYfgJyGImG2tsakmavSD4 X-Received: by 2002:a62:e0d8:: with SMTP id d85mr47214878pfm.214.1546516820256; Thu, 03 Jan 2019 04:00:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546516820; cv=none; d=google.com; s=arc-20160816; b=DiC0gvyGcxhyZdhwdFNLNZeg2XmgsiIq9b+weLFzLfvghQjNLCOX4Gqpuyb+EyE+ZD 57Fgu0YHWPekw6Q/rKeEmWtYRyfSWYpr9SBxutsS0ZIOCSwjYNw4HQUI+ESX2hXNMnhu yUZ4Lg+dGWlF9ZCydKSnR/T4ePVqHgXRCgMRO7jCB7IQ3ig/AEZvpCpMxSDhWk4U/680 ARZNmJIriFjH/n2GY2LSwr3xQq9lg6YFUHuoIDGH4nhkPsJTMs8b7A69+2KXbIsTt+yt 0Y4FtKWe7WQpHIU3wPOZzGaI/4kDTUOULSHHxaxRfSvUim3yjVis3k1FMxOVJDD1PUzL GtMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:delivered-to; bh=jb5MauPGd3lLvayTAp2yCNnrWNON3aAbFDh89BdJUFY=; b=HnYlvRQE32HW0CleP8kmblBx+7GjASoDU+UjrWsri4f5HbCPpYlH8JftSJp8JjkCYn zO2gLrTgqaG5M0yX0sSouEwlP97qxv5/XjNeYiVRxs8UFbZCgmdYRkMY85ww+JFoFiWr rximxW2sfmAXVQ59U9uddZcBahaMwuxR+UEm1IlRUwit96pqF590HcY70IF9d8HD9RmM 5vP8K4CPOGnft4Kk7YaIBOL1AZWdXIU5pHkzs8A0EnpeC+SPOwbANB0gx5lT2F+Eil+6 +pfLyeArLlpePFJniVPbXZd5Pkex6jxEpFI01uoPs/6TBu+7oUdnv4GmTgvwbLt7U84q /fxw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id f13si33940631pln.368.2019.01.03.04.00.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Jan 2019 04:00:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BBD166EAD2; Thu, 3 Jan 2019 12:00:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by gabe.freedesktop.org (Postfix) with ESMTPS id C46F36EAD2 for ; Thu, 3 Jan 2019 12:00:17 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x03C0DiD081973; Thu, 3 Jan 2019 06:00:13 -0600 Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x03C0DoH029623 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Jan 2019 06:00:13 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 3 Jan 2019 06:00:12 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 3 Jan 2019 06:00:12 -0600 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x03Bxxgl001514; Thu, 3 Jan 2019 06:00:11 -0600 From: Tomi Valkeinen To: Archit Taneja , Andrzej Hajda , , Andrey Gusakov Subject: [PATCHv2 6/7] drm/bridge: tc358767: fix output H/V syncs Date: Thu, 3 Jan 2019 13:59:53 +0200 Message-ID: <20190103115954.12785-7-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190103115954.12785-1-tomi.valkeinen@ti.com> References: <20190103115954.12785-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The H and V syncs of the DP output are always set to active high. This patch fixes the syncs by configuring them according to the videomode. Signed-off-by: Tomi Valkeinen Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/bridge/tc358767.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index a1f3dd2afbb1..391547358756 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -98,6 +98,8 @@ #define DP0_STARTVAL 0x064c #define DP0_ACTIVEVAL 0x0650 #define DP0_SYNCVAL 0x0654 +#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) +#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) #define DP0_MISC 0x0658 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ #define BPC_6 (0 << 5) @@ -726,7 +728,9 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode) tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); - tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0)); + tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) | + ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | + ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);