From patchwork Tue Mar 6 13:55:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 130801 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp3966971lja; Tue, 6 Mar 2018 05:57:12 -0800 (PST) X-Google-Smtp-Source: AG47ELuDfkCevt/f0QCcf9iEjzt7xDD1ois9Yvy4K5FMKeUiE1PKiq5iA0tkTUy+K0CZAR7eX3YY X-Received: by 10.101.93.73 with SMTP id e9mr15416627pgt.264.1520344632060; Tue, 06 Mar 2018 05:57:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520344632; cv=none; d=google.com; s=arc-20160816; b=wfBobn/c5ZiMytliD4DzsSxrza7Na4pzQ6pC/7Sjz4GDVQRyRZ2b+cFDnEm4G6Gfq4 QFsLgVNv46HZUQh6rsTVTPD7Vmx9Fec75TojODDGYIysJqLLPb2JxkeJWkOpsxS9g2Lr 7r3hSCMy/cu3ttKMNxGe40mupne8y8brduZZSFg6HU05tlnfSBtiXULSGsOfHOXtTyh/ bkU4yzJwl5urQBs4ahYuQiwTHKwTLYl7G83ENeKw33re3zXhYPWA5unr3ihj1jB39BKU e/uRfddbhjQSxu7sGNdNQrIxLocVzEY5bMK3WumxXf/GubSwirw//rjQ1YrRBmfXyVoU 1m/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:references:in-reply-to:references:in-reply-to :message-id:date:subject:to:from:delivered-to :arc-authentication-results; bh=ooCVOwwl67X/qzTq/dSVOhxGu/m6rS4W6kQFcDLpK3A=; b=utk8avbzrJ6juo0FwUz/dPCCE0NDDcZzNwDFazIFrUu2VmkyCHRxP+F+9JnomGWzYK yHU3RUf1vFCuB5tvoHbv2xfuJBmlgbWP2VtToyh24CfnnvRonybQeFZecZyuJV93usLH zZA/EPPPR/H8m8vkoCB6Y8C2V+7LI2vv9mzIW/Eb1tuJZhOw/48HumexoYuUHoBy2sLB XeUKKW43jdTZVtcNeYFk7tKnWsR0UT8pXrefqaKX1+lrRo8vcHKt9f/Arv9kuj3RsrFm bizUPBevKAz4giTDMce+ZLWOGisdPlkrAvRlFnRRy6Xlc+hE2it6mYFObHllijXiIbGN b43g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id d17-v6si8028036pls.822.2018.03.06.05.57.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Mar 2018 05:57:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 20F1F6E08F; Tue, 6 Mar 2018 13:57:11 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.bootlin.com (mail.bootlin.com [62.4.15.54]) by gabe.freedesktop.org (Postfix) with ESMTP id A78EF6E08F for ; Tue, 6 Mar 2018 13:57:09 +0000 (UTC) Received: by mail.bootlin.com (Postfix, from userid 110) id A235D20713; Tue, 6 Mar 2018 14:57:07 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (unknown [185.94.189.190]) by mail.bootlin.com (Postfix) with ESMTPSA id BA7B0207DA; Tue, 6 Mar 2018 14:56:15 +0100 (CET) From: Maxime Ripard To: Thierry Reding , Chen-Yu Tsai , Maxime Ripard , Mark Rutland , Rob Herring Subject: [PATCH v3 2/7] dt-bindings: display: Add Allwinner MIPI-DSI bindings Date: Tue, 6 Mar 2018 14:55:59 +0100 Message-Id: <5f183ae295c0190369ec576ecfb10c1d78f41eb3.1520344489.git-series.maxime.ripard@bootlin.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Thomas Petazzoni , Daniel Vetter , Maxime Ripard , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Maxime Ripard The Allwinner SoCs usually come with a DSI encoder. Add a binding for it. Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 93 +++++++- 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt new file mode 100644 index 000000000000..6a6cf5de08b0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt @@ -0,0 +1,93 @@ +Allwinner A31 DSI Encoder +========================= + +The DSI pipeline consists of two separate blocks: the DSI controller +itself, and its associated D-PHY. + +DSI Encoder +----------- + +The DSI Encoder generates the DSI signal from the TCON's. + +Required properties: + - compatible: value must be one of: + * allwinner,sun6i-a31-mipi-dsi + - reg: base address and size of memory-mapped region + - interrupts: interrupt associated to this IP + - clocks: phandles to the clocks feeding the DSI encoder + * bus: the DSI interface clock + * mod: the DSI module clock + - clock-names: the clock names mentioned above + - phys: phandle to the D-PHY + - phy-names: must be "dphy" + - resets: phandle to the reset controller driving the encoder + + - ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoint, usually coming from the + associated TCON. + +Any MIPI-DSI device attached to this should be described according to +the bindings defined in ../mipi-dsi-bus.txt + +D-PHY +----- + +Required properties: + - compatible: value must be one of: + * allwinner,sun6i-a31-mipi-dphy + - reg: base address and size of memory-mapped region + - clocks: phandles to the clocks feeding the DSI encoder + * bus: the DSI interface clock + * mod: the DSI module clock + - clock-names: the clock names mentioned above + - resets: phandle to the reset controller driving the encoder + +Example: + +dsi0: dsi@1ca0000 { + compatible = "allwinner,sun6i-a31-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy0>; + phy-names = "dphy"; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; + reg = <0>; + power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */ + reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ + backlight = <&pwm_bl>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dsi0_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi0>; + }; + }; + }; +}; + +dphy0: d-phy@1ca1000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + #phy-cells = <0>; +};