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[209.132.180.131]) by mx.google.com with ESMTPS id 207si2901284pfc.55.2017.02.21.08.54.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Feb 2017 08:54:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-448905-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-448905-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-448905-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=qsY0kYatD1ki OCod/07JHZSKsbJh44+jPngXGkqnc6yCgxWl2yF1AXISYp2r9eClOd9zMwT4CNrh NPEcwlhzLNBGex2OBEAubK2JQagYRD+25wuaJT2OYS9xoPvMLed4EVCUOf5sJayx WSyhKTy5GNGCc1pKdvsgh5isad5qPLk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=eY0MYF6TGv6IVgNrWw NiTDsdukE=; b=wZLfi7MLDU0uHULlLhi3P46WuJyvjgaDvZ/R6RuQzp+QvW+pKZ jDQQgLNAx6PnVoX7IWjSMzQLTfciw+j12T9cKImapmMsSqjFIZX1E7CeITU7Oj2O 6C1oCMUPvSxZx+06yXPDqvntRmvHYtePyBiL/JhW30GAnVIBHCRtYtEYg= Received: (qmail 115239 invoked by alias); 21 Feb 2017 16:54:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115218 invoked by uid 89); 21 Feb 2017 16:54:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:charles, HX-Envelope-From:sk:charles, CortexA57, cortex-a57 X-HELO: mail-wm0-f53.google.com Received: from mail-wm0-f53.google.com (HELO mail-wm0-f53.google.com) (74.125.82.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 Feb 2017 16:54:32 +0000 Received: by mail-wm0-f53.google.com with SMTP id v77so80694319wmv.0 for ; Tue, 21 Feb 2017 08:54:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=uw2ml6hlSY6Ey1X6PxhH4i9FtQtXYIGQzYvR0bVzLdU=; b=m8I1HZ+yI0ic39b157+NoqqSMHDySADI8cESjFLo5Vrafd7Et6e+Tqz0j+beVxmlYb 0kdTknzmXYl0qJZho+DJBlybp6mbhz55xcEcN/8lj1V6wYeWpjgsNfdE4xemtign295F mYqQjyF4ojdNg6V1VwmAHc6rHL92pl9HUlqeDdhEiYHkpKgNN2xoirVKmvHZPRiPITYd aMBkVJMjMnSwpi4E+0UH288h8Ubvd4XCqZeCxlqHaL8My27vooerO3I1tM9+TI6IWrwq 6lqvekCm29s+dbc6KSDfHZYAKrnlBBgpN8ucNNS3y4elXXVevFZLNWSYgFMfo/qa3mKo W2Ag== X-Gm-Message-State: AMke39lrGX5ZWe1ZRaUgeJ+BB4vb4VVbXBvs+2OiSDWSf+JBnI2GqXlphF0zy/QJkrSyUvWl X-Received: by 10.28.97.2 with SMTP id v2mr27344030wmb.3.1487696070445; Tue, 21 Feb 2017 08:54:30 -0800 (PST) Received: from localhost.localdomain ([85.255.232.30]) by smtp.gmail.com with ESMTPSA id i73sm18293060wmd.11.2017.02.21.08.54.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Feb 2017 08:54:29 -0800 (PST) From: charles.baylis@linaro.org To: Ramana.Radhakrishnan@arm.com, kyrylo.tkachov@arm.com Cc: rearnsha@arm.com, gcc-patches@gcc.gnu.org Subject: [PATCH 0/2] [ARM] PR61551 addressing mode costs Date: Tue, 21 Feb 2017 16:54:22 +0000 Message-Id: <1487696064-3233-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis Hi Ramana, This patch set continues previous work on fixing the cost calculations for MEMs which use different addressing modes. It implements the approach we discussed at Linaro Connect BKK16. I have included some notes on the patch set as follows: Background: The motivating problem is that this function: char *f(char *p, int8x8x4_t v, int r) { vst4_s8(p, v); p+=32; return p; } compiles to: mov r3, r0 adds r0, r0, #32 vst4.8 {d0-d3}, [r3] bx lr but we would like to get: vst4.8 {d0-d3}, [r0]! bx lr Although the ARM back end contains patterns for the write-back forms of these instructions, they are not currently generated. The reason for this is that the auto-inc-dec phase does not perform this optimisation because arm_rtx_costs incorrectly calculates the cost of "vst4.8 {d0-d3}, [r0]!" as much higher than "vst4.8 {d0-d3}, [r3]". For that reason, it considers the POST_INC form to be worse than the initial sequence of vst4/add and does not perform the transformation. In fact, GCC6 has regressions compared to GCC5 in this area, and no longer does post-indexed addressing for int64_t or 64 bit vector types. Solution: Change cost calculation for MEMs so that the cost of the memory access is computed separately from the cost of the addressing mode. A new table-driven mechanism is introduced for the costs of the addressing modes. The first patch in the series implements the calculation of the cost of the memory access. The second patch adds the table-driven model of the extra cost of the selected addressing mode. I don't have access to a lot of CPU pipeline information, so most CPUs use the generic cost table, with the exception of Cortex-A57. Testing: I did "make check" on arm-linux-gnueabihf with qemu. This patch fixes one test failure in lp1243022.c. Benchmarking: On Cortex-A15, SPEC2006 and a popular suite of embedded benchmarks perform the same as before this patch is applied. This is expected, the expected gain is in code quality for hand-written NEON intrinsics code. Charles Baylis (2): [ARM] Refactor costs calculation for MEM. [ARM] Add table of costs for AAarch32 addressing modes. gcc/config/arm/aarch-common-protos.h | 16 +++++ gcc/config/arm/aarch-cost-tables.h | 54 ++++++++++++++-- gcc/config/arm/arm.c | 120 ++++++++++++++++++++++++++--------- 3 files changed, 154 insertions(+), 36 deletions(-) -- 2.7.4