Show patches with: Archived = No       |   3544 patches
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Patch Series S/W/F Date Submitter Delegate State
[0/7] Type promotion pass and elimination of zext/sext --- 2015-11-12 Kugan Vivekanandarajah Superseded
[ARM/Aarch64] add initial Qualcomm support --- 2015-11-11 Jim Wilson New
[ARM] Do not expand movmisalign pattern if not in 32-bit mode --- 2015-11-11 Kyrylo Tkachov New
[4b/4,ARM] PR63870 Remove error for invalid lane numbers --- 2015-11-11 Charles Baylis New
[ARM] PR 68149 Fix ICE in unaligned_loaddi split --- 2015-11-10 Kyrylo Tkachov New
[5/Vect] Partial backport of r228751 (pr68238) --- 2015-11-10 James Greenhalgh New
[ARM,3/3,v2] Implement negsicc, notsicc optabs --- 2015-11-10 Kyrylo Tkachov New
[haifa-sched] PR rtl-optimization/68236: Exit early from autoprefetcher lookahead if not in haifa sched --- 2015-11-09 Kyrylo Tkachov Accepted
[AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INT --- 2015-11-09 Kyrylo Tkachov Accepted
[optabs,ifcvt,1/3] Define negcc, notcc optabs --- 2015-11-09 Kyrylo Tkachov New
[ARM] Use snprintf rather than sprintf where possible --- 2015-11-09 Kyrylo Tkachov New
[AArch64,cleanup] Remove uses of CONST_DOUBLE_HIGH, CONST_DOUBLE_LOW --- 2015-11-09 Kyrylo Tkachov New
[AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INT --- 2015-11-09 Kyrylo Tkachov Superseded
[Aarch64] Use vector wide add for mixed-mode adds --- 2015-11-09 Michael Collison Superseded
[0/7] Type promotion pass and elimination of zext/sext --- 2015-11-08 Kugan Vivekanandarajah Superseded
[4b/4,ARM] PR63870 Remove error for invalid lane numbers --- 2015-11-08 Charles Baylis New
[4a/4,ARM] PR63870 Use internal_error() for invalid lane numbers --- 2015-11-08 Charles Baylis New
[3/4,ARM] PR63870 Add test cases --- 2015-11-08 Charles Baylis New
[2/4,ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier --- 2015-11-08 Charles Baylis New
[1/4,ARM] PR63870 Add qualifiers for NEON builtins --- 2015-11-08 Charles Baylis Superseded
[ARM] PR 49526: Add support for smmul,smmla,smmls instructions --- 2015-11-06 Kyrylo Tkachov New
[Obivous,testsuite,aarch64/arm] Fix typo --- 2015-11-06 Christophe Lyon New
[combine,RFC] Don't transform sign and zero extends inside mults --- 2015-11-06 Kyrylo Tkachov New
[AArch64] Fix vqtb[lx][234] on big-endian --- 2015-11-06 Christophe Lyon New
[cp,committed] Fix bootstrap on arm due to print format warning --- 2015-11-06 Kyrylo Tkachov New
[ARM] PR 68143 Properly update memory offsets when expanding setmem --- 2015-11-06 Kyrylo Tkachov Superseded
[ARM,PR,68223] arm_[su]min_cmp pattern fails --- 2015-11-06 Michael Collison New
[ARM,cleanup] Remove uses of CONST_DOUBLE_HIGH/LOW --- 2015-11-05 Kyrylo Tkachov New
[ARM] PR61551 RFC: Improve costs for NEON addressing modes --- 2015-11-04 Charles Baylis New
[ifcvt] Teach RTL ifcvt to handle multiple simple set instructions --- 2015-11-04 James Greenhalgh New
[AArch64,v2] Improve comparison with complex immediates followed by branch/cset --- 2015-11-03 Kyrylo Tkachov Superseded
[combine,RFC] Don't transform sign and zero extends inside mults --- 2015-11-02 Kyrylo Tkachov New
[ARM] PR target/67929 Tighten vfp3_const_double_for_bits checks --- 2015-11-02 Kyrylo Tkachov New
[0/7] Type promotion pass and elimination of zext/sext --- 2015-11-02 Kugan Vivekanandarajah Superseded
[ARM] PR61551 RFC: Improve costs for NEON addressing modes --- 2015-10-31 Charles Baylis New
[ifcvt] Teach RTL ifcvt to handle multiple simple set instructions --- 2015-10-30 James Greenhalgh Superseded
[ARM] Fix checking RTL error in cortex_a9_sched_adjust_cost --- 2015-10-30 Kyrylo Tkachov New
[ARM] neon-testgen.ml typo --- 2015-10-29 Jim Wilson New
[Docs] Reword the documentation for -fdump-rtl- --- 2015-10-29 James Greenhalgh New
[ARM] Fix checking RTL error in cortex_a9_sched_adjust_cost --- 2015-10-29 Kyrylo Tkachov Accepted
[Docs] Reword the documentation for -fdump-rtl- --- 2015-10-29 James Greenhalgh Superseded
[ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check --- 2015-10-29 Kyrylo Tkachov New
[ARM] libgcc: include crtfastmath.o --- 2015-10-29 Christophe Lyon New
[C] fix for ICE with -g --- 2015-10-28 Jim Wilson New
[RFC,tree-ifcombine] Making tree-ifcombine more friendly for conditional comparisons generation --- 2015-10-28 Kyrylo Tkachov New
[ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check --- 2015-10-28 Kyrylo Tkachov New
[AArch64] Handle vector float modes properly in aarch64_output_simd_mov_immediate --- 2015-10-27 Kyrylo Tkachov Accepted
[AArch64] PR 68102: Check that operand is REG before checking the REGNO in mov-immediate splitters --- 2015-10-27 Kyrylo Tkachov Accepted
[RTL-ifcvt] PR rtl-optimization/67749: Do not emit separate SET insn in IF-ELSE case --- 2015-10-27 Kyrylo Tkachov Accepted
[ARM] Fix costing of vmul+vcvt combine pattern --- 2015-10-27 Kyrylo Tkachov Accepted
[wwwdocs] Mention arm target attributes and pragmas in GCC 6 changes --- 2015-10-26 Kyrylo Tkachov New
[auto-inc-dec.c] Account for cost of move operation in FORM_PRE_ADD and FORM_POST_ADD cases --- 2015-10-26 Kyrylo Tkachov Accepted
[auto-inc-dec.c] Account for cost of move operation in FORM_PRE_ADD and FORM_POST_ADD cases --- 2015-10-26 Kyrylo Tkachov Superseded
[optabs.c] Fix PR 67989: Handle const0_rtx target in expand_atomic_compare_and_swap --- 2015-10-22 Kyrylo Tkachov Accepted
[AArch64] Enable autoprefetcher modelling in the scheduler --- 2015-10-22 Kyrylo Tkachov Accepted
[AArch64] support -mfentry feature for arm64 --- 2015-10-22 Li Bin Superseded
[0/7] Type promotion pass and elimination of zext/sext --- 2015-10-22 Kugan Vivekanandarajah Superseded
[simplify-rtx,2/2] Use constants from pool when simplifying binops --- 2015-10-20 Kyrylo Tkachov New
[AArch64,1/2] Add fmul-by-power-of-2+fcvt optimisation --- 2015-10-20 Kyrylo Tkachov New
[AArch64] Fix insn types --- 2015-10-20 Kyrylo Tkachov New
[simplify-rtx,2/2] Use constants from pool when simplifying binops --- 2015-10-19 Kyrylo Tkachov New
[AArch64,1/2] Add fmul-by-power-of-2+fcvt optimisation --- 2015-10-19 Kyrylo Tkachov New
[5/7] Allow gimple debug stmt in widen mode --- 2015-10-18 Kugan Vivekanandarajah New
[AArch64] Add support for 64-bit vector-mode ldp/stp --- 2015-10-16 Kyrylo Tkachov Accepted
[AArch64,63304] Fix issue with global state. --- 2015-10-16 Ramana Radhakrishnan New
[testsuite] Fix potential race conditions in gfortran tests --- 2015-10-16 Christophe Lyon New
[haifa-sched] model load/store multiples properly in autoprefetcher scheduling --- 2015-10-15 Kyrylo Tkachov Accepted
[haifa-sched] model load/store multiples properly in autoprefetcher scheduling --- 2015-10-15 Kyrylo Tkachov Superseded
[2/7] Add new type promotion pass --- 2015-10-15 Kugan Vivekanandarajah New
[1/7] Add new tree code SEXT_EXPR --- 2015-10-15 Kugan Vivekanandarajah New
[5/7] Allow gimple debug stmt in widen mode --- 2015-10-15 Kugan Vivekanandarajah New
[ARM,4.9/5,Backport] PR target/67929 Tighten vfp3_const_double_for_bits checks --- 2015-10-14 Kyrylo Tkachov New
[ARM] PR target/67929 Tighten vfp3_const_double_for_bits checks --- 2015-10-14 Kyrylo Tkachov Accepted
[AArch64_be] Fix vtbl[34] and vtbx4 --- 2015-10-13 Christophe Lyon New
[1/7] Add new tree code SEXT_EXPR --- 2015-10-11 Kugan Vivekanandarajah New
[3/7] Optimize ZEXT_EXPR with tree-vrp --- 2015-10-11 Kugan Vivekanandarajah New
[AArch64_be] Fix vtbl[34] and vtbx4 --- 2015-10-09 Christophe Lyon Accepted
[PR,target/67366,2/2,gimple-fold.c] Support movmisalign optabs in gimple-fold.c --- 2015-10-08 Ramana Radhakrishnan New
[PR,target/67366,1/2,ARM] - Add movmisalignhi / si patterns --- 2015-10-08 Ramana Radhakrishnan New
[AArch64] Improve comparison with complex immediates followed by branch/cset --- 2015-10-08 Kyrylo Tkachov Superseded
[3/7] Optimize ZEXT_EXPR with tree-vrp --- 2015-10-07 Kugan Vivekanandarajah New
[3/3,ARM] PR63870 Enable test cases --- 2015-10-06 Charles Baylis New
[2/3,ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier --- 2015-10-06 Charles Baylis Superseded
[1/3,ARM] PR63870 Add qualifiers for NEON builtins --- 2015-10-06 Charles Baylis Superseded
[3/7] Optimize ZEXT_EXPR with tree-vrp --- 2015-10-06 Kugan Vivekanandarajah New
[AARCH64] Add missing entries in iterator vwcore --- 2015-10-06 Kugan Vivekanandarajah New
[ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code --- 2015-10-02 Kyrylo Tkachov New
[AArch64] Use default_elf_asm_named_section instead of special cased hook --- 2015-10-02 Ramana Radhakrishnan Accepted
[AArch64] Improve SIMD concatenation with zeroes --- 2015-10-02 James Greenhalgh New
[AARCH64] Add missing entries in iterator vwcore --- 2015-10-01 Kugan Vivekanandarajah New
[match.pd] Add a simplify rule for x * copysign (1.0, y); --- 2015-10-01 James Greenhalgh New
[RTL,ifcvt] PR 67786, 67787: Check that intermediate instructions in the basic block don't clobber a reg used in condition --- 2015-10-01 Kyrylo Tkachov Accepted
[AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives --- 2015-10-01 Kyrylo Tkachov Accepted
[ARM] Use vector wide add for mixed-mode adds --- 2015-10-01 Michael Collison New
[2/2,ARM/AArch64] Add a new Cortex-A53 scheduling model --- 2015-10-01 James Greenhalgh Accepted
Optimize certain end of loop conditions into min/max operation --- 2015-10-01 Michael Collison New
Optimize certain end of loop conditions into min/max operation --- 2015-10-01 Michael Collison New
Optimize certain end of loop conditions into min/max operation --- 2015-10-01 Michael Collison New
[ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code --- 2015-09-30 Kyrylo Tkachov New
Optimize certain end of loop conditions into min/max operation --- 2015-09-30 Michael Collison New
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