[06/30,arm] Add default FPUs for CPUs.

Message ID	0f3e9a9755d3d1b249e7a592695b43c64427150d.1497004220.git.Richard.Earnshaw@arm.com
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of gcc-patches-return-455524-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=T9/VtK0VKWNUIUk5CiId9rTg+6jkQJ8aieyT1T95TcoW+0H6VPWvh UNPle6T9TbOah0LnS2LAsoahQpG/6aJbHfsjonVwHKg+sT0tf5IQrw0a2oZU/yF4 Nn/t5kC+d6xSAjiaqwy3nEq9BkzC1oQkijd/QmtBDby7pn9By53G+Y= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: Richard Earnshaw <Richard.Earnshaw@arm.com> To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw <Richard.Earnshaw@arm.com> Subject: [PATCH 06/30] [arm] Add default FPUs for CPUs. Date: Fri, 9 Jun 2017 13:53:35 +0100 Message-Id: <0f3e9a9755d3d1b249e7a592695b43c64427150d.1497004220.git.Richard.Earnshaw@arm.com> In-Reply-To: <cover.1497004220.git.Richard.Earnshaw@arm.com> References: <cover.1497004220.git.Richard.Earnshaw@arm.com> In-Reply-To: <cover.1497004220.git.Richard.Earnshaw@arm.com> References: <cover.1497004220.git.Richard.Earnshaw@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.7.4"
Series	Reworking the -mcpu, -march and -mfpu options \| expand [00/30,ARM] Reworking the -mcpu, -march and -mfpu options [01/30,arm] Use strings for -march, -mcpu and -mtune options [02/30,arm] Rewrite -march and -mcpu options for passing to the assembler [03/30,arm] Don't pass -mfpu=auto through to the assembler. [04/30,arm] Allow +opt on arbitrary cpu and architecture specifications [05/30,arm] Add architectural options [06/30,arm] Add default FPUs for CPUs. [07/30,build] Make sbitmap code available to the driver programs [08/30,arm] Split CPU, architecture and tuning data tables. [09/30,ARM] Move cpu and architecture option name parsing code to arm-common.c [10/30,arm] Use standard option parsing code for detecting thumb-only targets [11/30,arm] Allow CPU and architecture extensions to be defined as aliases [12/30,arm] Allow new extended syntax CPU and architecture names during configure [13/30,arm] Force a CPU default in the config args defaults list. [14/30,arm] Generate a canonical form for -march [15/30,arm] Make -mfloat-abi=softfp work when there are no FPU instructions [16/30,arm] Update basic multilib configuration [17/30,arm] Make 'auto' the default FPU selection option. [18/30,arm] Rewrite t-aprofile using new selector methodology [19/30,arm] Explicitly set .fpu in cmse_nonsecure_call.S [20/30,genmultilib] Allow explicit periods to be escaped in MULTILIB_REUSE [21/30,arm,testsuite] Use -march=armv7-a+fp when testing hard-float ABI. [22/30,arm] Rewrite t-rmprofile multilib specification [23/30,arm,rtems] Update t-rtems for new option framework [24/30,arm,linux-eabi] Ensure all multilib variables are reset [25/30,arm,phoenix] reset all multilib variables [26/30,arm] Rework multlib builds for symbianelf [27/30,arm,fuchsia] Rework multilib support [28/30,arm] Add a few missing architecture extension options. [29/30,arm,doc] Document new -march= syntax. [30/30,arm,doc] Document changes to -mcpu, -mtune and -mfpu.

diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index 878d226..3be0b78 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -341,6 +341,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm9e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -348,6 +349,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm946e-s", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -355,6 +357,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm966e-s", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -362,6 +365,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm968e-s", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -369,6 +373,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm10e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -376,6 +381,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm1020e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -383,6 +389,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm1022e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -440,6 +447,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm926ej-s", { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -447,6 +455,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm1026ej-s", { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -556,6 +565,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "generic-armv7-a", { ISA_ARMv7a, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -563,6 +573,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a5", { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, }, @@ -570,6 +581,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a7", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -585,7 +597,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a9", { ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, }, @@ -593,6 +605,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a12", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -600,6 +613,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a15", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -607,6 +621,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a17", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -621,6 +636,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r4f", { ISA_ARMv7r, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -628,7 +644,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r5", { ISA_ARMv7r, - isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -636,7 +652,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r7", { ISA_ARMv7r, - isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -644,7 +660,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r8", { ISA_ARMv7r, - isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -652,6 +668,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-m7", { ISA_ARMv7em, + ISA_FPv5,ISA_FP_DBL, isa_quirk_no_volatile_ce, isa_nobit }, @@ -660,6 +677,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-m4", { ISA_ARMv7em, + ISA_VFPv4, isa_nobit }, }, @@ -682,6 +700,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a15.cortex-a7", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -689,6 +708,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a17.cortex-a7", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -696,6 +716,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a32", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -703,6 +724,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a35", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -710,6 +732,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -717,6 +740,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a57", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -724,6 +748,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a72", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -731,6 +756,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a73", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -738,6 +764,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "exynos-m1", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -745,6 +772,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "falkor", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -752,6 +780,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "qdf24xx", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -759,6 +788,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "xgene1", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -766,6 +796,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a57.cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -773,6 +804,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a72.cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -780,6 +812,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a73.cortex-a35", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -787,6 +820,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a73.cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -801,6 +835,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-m33", { ISA_ARMv8m_main, + ISA_FPv5, isa_nobit }, }, diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 21d4f82..da9d273 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -20,10 +20,162 @@ License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +static const struct cpu_option cpu_opttab_arm9e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm946es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm966es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm968es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm10e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm1020e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm1022e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm926ejs[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm1026ejs[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_genericv7a[] = { + { + "simd", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "vfpv3", false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-fp16", false, + { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv3-d16-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "neon", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv3", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-fp16", false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + }, + { + "neon-vfpv4", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa5[] = { + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa7[] = { + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + static const struct cpu_option cpu_opttab_cortexa8[] = { { "nofp", true, - { ISA_NEON,ISA_VFPv3, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -31,11 +183,231 @@ static const struct cpu_option cpu_opttab_cortexa8[] = { static const struct cpu_option cpu_opttab_cortexa9[] = { { "nofp", true, - { ISA_NEON,ISA_VFPv3, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nosimd", true, - { ISA_NEON, isa_nobit } + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa12[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa15[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa17[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexr5[] = { + { + "nofp.dp", true, + { ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexr7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexr8[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexm7[] = { + { + "nofp.dp", true, + { ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexm4[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa15cortexa7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa17cortexa7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa32[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa35[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa57[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa72[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa73[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_exynosm1[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_falkor[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_qdf24xx[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_xgene1[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa57cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa72cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa73cortexa35[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa73cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexm33[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -589,9 +961,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm9e, &arm_9e_tune }, { @@ -601,9 +974,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm946es, &arm_9e_tune }, { @@ -613,9 +987,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm966es, &arm_9e_tune }, { @@ -625,9 +1000,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm968es, &arm_9e_tune }, { @@ -637,9 +1013,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm10e, &arm_fastmul_tune }, { @@ -649,9 +1026,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm1020e, &arm_fastmul_tune }, { @@ -661,9 +1039,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm1022e, &arm_fastmul_tune }, { @@ -758,9 +1137,10 @@ static const struct processors all_cores[] = "5TEJ", BASE_ARCH_5TEJ, { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm926ejs, &arm_9e_tune }, { @@ -770,9 +1150,10 @@ static const struct processors all_cores[] = "5TEJ", BASE_ARCH_5TEJ, { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm1026ejs, &arm_9e_tune }, { @@ -954,9 +1335,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_genericv7a, &arm_cortex_tune }, { @@ -966,9 +1348,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, - NULL, + cpu_opttab_cortexa5, &arm_cortex_a5_tune }, { @@ -978,9 +1361,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa7, &arm_cortex_a7_tune }, { @@ -1003,7 +1387,7 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, cpu_opttab_cortexa9, @@ -1016,9 +1400,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa12, &arm_cortex_a12_tune }, { @@ -1028,9 +1413,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa15, &arm_cortex_a15_tune }, { @@ -1040,9 +1426,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa17, &arm_cortex_a12_tune }, { @@ -1064,6 +1451,7 @@ static const struct processors all_cores[] = "7R", BASE_ARCH_7R, { ISA_ARMv7r, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, NULL, @@ -1077,9 +1465,10 @@ static const struct processors all_cores[] = { ISA_ARMv7r, isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_cortexr5, &arm_cortex_tune }, { @@ -1090,9 +1479,10 @@ static const struct processors all_cores[] = { ISA_ARMv7r, isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_cortexr7, &arm_cortex_tune }, { @@ -1103,9 +1493,10 @@ static const struct processors all_cores[] = { ISA_ARMv7r, isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_cortexr8, &arm_cortex_tune }, { @@ -1115,10 +1506,11 @@ static const struct processors all_cores[] = "7EM", BASE_ARCH_7EM, { ISA_ARMv7em, + ISA_FPv5,ISA_FP_DBL, isa_quirk_no_volatile_ce, isa_nobit }, - NULL, + cpu_opttab_cortexm7, &arm_cortex_m7_tune }, { @@ -1128,9 +1520,10 @@ static const struct processors all_cores[] = "7EM", BASE_ARCH_7EM, { ISA_ARMv7em, + ISA_VFPv4, isa_nobit }, - NULL, + cpu_opttab_cortexm4, &arm_v7m_tune }, { @@ -1165,9 +1558,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa15cortexa7, &arm_cortex_a15_tune }, { @@ -1177,9 +1571,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa17cortexa7, &arm_cortex_a12_tune }, { @@ -1190,9 +1585,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa32, &arm_cortex_a35_tune }, { @@ -1203,9 +1599,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa35, &arm_cortex_a35_tune }, { @@ -1216,9 +1613,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa53, &arm_cortex_a53_tune }, { @@ -1229,9 +1627,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa57, &arm_cortex_a57_tune }, { @@ -1242,9 +1641,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa72, &arm_cortex_a57_tune }, { @@ -1255,9 +1655,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa73, &arm_cortex_a73_tune }, { @@ -1268,9 +1669,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_exynosm1, &arm_exynosm1_tune }, { @@ -1281,9 +1683,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_falkor, &arm_qdf24xx_tune }, { @@ -1294,9 +1697,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_qdf24xx, &arm_qdf24xx_tune }, { @@ -1306,9 +1710,10 @@ static const struct processors all_cores[] = "8A", BASE_ARCH_8A, { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_xgene1, &arm_xgene1_tune }, { @@ -1319,9 +1724,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa57cortexa53, &arm_cortex_a57_tune }, { @@ -1332,9 +1738,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa72cortexa53, &arm_cortex_a57_tune }, { @@ -1345,9 +1752,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa73cortexa35, &arm_cortex_a73_tune }, { @@ -1358,9 +1766,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa73cortexa53, &arm_cortex_a73_tune }, { @@ -1383,9 +1792,10 @@ static const struct processors all_cores[] = { ISA_ARMv8m_main, isa_bit_ARMv7em, + ISA_FPv5, isa_nobit }, - NULL, + cpu_opttab_cortexm33, &arm_v7m_tune }, {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL} @@ -1402,7 +1812,7 @@ static const struct cpu_option arch_opttab_armv5e[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1418,7 +1828,7 @@ static const struct cpu_option arch_opttab_armv5te[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1434,7 +1844,7 @@ static const struct cpu_option arch_opttab_armv5tej[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1450,7 +1860,7 @@ static const struct cpu_option arch_opttab_armv6[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1466,7 +1876,7 @@ static const struct cpu_option arch_opttab_armv6j[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1482,7 +1892,7 @@ static const struct cpu_option arch_opttab_armv6k[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1498,7 +1908,7 @@ static const struct cpu_option arch_opttab_armv6z[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1514,7 +1924,7 @@ static const struct cpu_option arch_opttab_armv6kz[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1530,7 +1940,7 @@ static const struct cpu_option arch_opttab_armv6zk[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1546,7 +1956,7 @@ static const struct cpu_option arch_opttab_armv6t2[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1569,18 +1979,14 @@ static const struct cpu_option arch_opttab_armv7_a[] = { { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "simd", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { "vfpv3", false, { ISA_VFPv3,ISA_FP_D32, isa_nobit } }, { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { "vfpv3-d16-fp16", false, { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } }, @@ -1589,12 +1995,16 @@ static const struct cpu_option arch_opttab_armv7_a[] = { { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } }, { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { "vfpv4", false, { ISA_VFPv4,ISA_FP_D32, isa_nobit } }, { - "vfpv4-d16", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + "simd", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } }, { "neon", false, @@ -1614,33 +2024,25 @@ static const struct cpu_option arch_opttab_armv7_a[] = { }, { "nofp", true, - { ISA_VFPv4,ISA_NEON, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nosimd", true, - { ISA_NEON, isa_nobit } + { ISA_ALL_SIMD, isa_nobit } }, { NULL, false, {isa_nobit}} }; static const struct cpu_option arch_opttab_armv7ve[] = { { - "fp", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "simd", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { "vfpv3", false, { ISA_VFPv3,ISA_FP_D32, isa_nobit } }, { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { "vfpv3-d16-fp16", false, { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } }, @@ -1649,14 +2051,18 @@ static const struct cpu_option arch_opttab_armv7ve[] = { { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } }, { - "vfpv4", false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, { - "vfpv4-d16", false, + "fp", false, { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { "neon", false, { ISA_VFPv3,ISA_NEON, isa_nobit } }, @@ -1669,36 +2075,40 @@ static const struct cpu_option arch_opttab_armv7ve[] = { { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } }, { + "simd", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { "neon-vfpv4", false, { ISA_VFPv4,ISA_NEON, isa_nobit } }, { "nofp", true, - { ISA_VFPv4,ISA_NEON, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nosimd", true, - { ISA_NEON, isa_nobit } + { ISA_ALL_SIMD, isa_nobit } }, { NULL, false, {isa_nobit}} }; static const struct cpu_option arch_opttab_armv7_r[] = { { - "fp", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { "fp.sp", false, { ISA_VFPv3, isa_nobit } }, { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { "idiv", false, { isa_bit_adiv, isa_nobit } }, { "nofp", true, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "noidiv", true, @@ -1722,7 +2132,7 @@ static const struct cpu_option arch_opttab_armv7e_m[] = { }, { "nofp", true, - { ISA_FPv5,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1738,15 +2148,15 @@ static const struct cpu_option arch_opttab_armv8_a[] = { }, { "crypto", false, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { "nofp", true, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nocrypto", true, - { ISA_CRYPTO, isa_nobit } + { ISA_ALL_CRYPTO, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1758,39 +2168,39 @@ static const struct cpu_option arch_opttab_armv8_1_a[] = { }, { "crypto", false, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { "nofp", true, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nocrypto", true, - { ISA_CRYPTO, isa_nobit } + { ISA_ALL_CRYPTO, isa_nobit } }, { NULL, false, {isa_nobit}} }; static const struct cpu_option arch_opttab_armv8_2_a[] = { { - "fp16", false, - { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { "simd", false, { ISA_FP_ARMv8,ISA_NEON, isa_nobit } }, { + "fp16", false, + { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { "crypto", false, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { "nofp", true, - { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nocrypto", true, - { ISA_CRYPTO, isa_nobit } + { ISA_ALL_CRYPTO, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1810,7 +2220,7 @@ static const struct cpu_option arch_opttab_armv8_m_main[] = { }, { "nofp", true, - { ISA_FPv5, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 4007c15..5a3a348 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -115,7 +115,7 @@ begin arch armv5e isa ARMv5e option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv5e begin arch armv5te @@ -125,7 +125,7 @@ begin arch armv5te isa ARMv5te option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv5te begin arch armv5tej @@ -135,7 +135,7 @@ begin arch armv5tej isa ARMv5tej option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv5tej begin arch armv6 @@ -145,7 +145,7 @@ begin arch armv6 isa ARMv6 option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6 begin arch armv6j @@ -155,7 +155,7 @@ begin arch armv6j isa ARMv6j option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6j begin arch armv6k @@ -165,7 +165,7 @@ begin arch armv6k isa ARMv6k option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6k begin arch armv6z @@ -175,7 +175,7 @@ begin arch armv6z isa ARMv6z option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6z begin arch armv6kz @@ -185,7 +185,7 @@ begin arch armv6kz isa ARMv6kz option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6kz begin arch armv6zk @@ -195,7 +195,7 @@ begin arch armv6zk isa ARMv6kz option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6zk begin arch armv6t2 @@ -205,7 +205,7 @@ begin arch armv6t2 isa ARMv6t2 option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6t2 begin arch armv6-m @@ -236,20 +236,20 @@ begin arch armv7-a base 7A isa ARMv7a # fp => VFPv3-d16, simd => neon-vfpv3 - option fp add VFPv3 FP_DBL - option simd add VFPv3 NEON - option vfpv3 add VFPv3 FP_D32 - option vfpv3-d16 add VFPv3 FP_DBL + option fp add VFPv3 FP_DBL + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3 add VFPv3 FP_D32 option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv - option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv - option vfpv4 add VFPv4 FP_D32 - option vfpv4-d16 add VFPv4 FP_DBL - option neon add VFPv3 NEON - option neon-vfpv3 add VFPv3 NEON - option neon-fp16 add VFPv3 NEON bit_fp16conv - option neon-vfpv4 add VFPv4 NEON - option nofp remove VFPv4 NEON - option nosimd remove NEON + option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv + option vfpv4-d16 add VFPv4 FP_DBL + option vfpv4 add VFPv4 FP_D32 + option simd add VFPv3 NEON + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option neon-vfpv4 add VFPv4 NEON + option nofp remove ALL_FP + option nosimd remove ALL_SIMD end arch armv7-a begin arch armv7ve @@ -258,20 +258,20 @@ begin arch armv7ve base 7A isa ARMv7ve # fp => VFPv4-d16, simd => neon-vfpv4 - option fp add VFPv4 FP_DBL - option simd add VFPv4 NEON - option vfpv3 add VFPv3 FP_D32 - option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3 add VFPv3 FP_D32 option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv - option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv - option vfpv4 add VFPv4 FP_D32 - option vfpv4-d16 add VFPv4 FP_DBL - option neon add VFPv3 NEON - option neon-vfpv3 add VFPv3 NEON - option neon-fp16 add VFPv3 NEON bit_fp16conv - option neon-vfpv4 add VFPv4 NEON - option nofp remove VFPv4 NEON - option nosimd remove NEON + option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv + option vfpv4-d16 add VFPv4 FP_DBL + option fp add VFPv4 FP_DBL + option vfpv4 add VFPv4 FP_D32 + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option simd add VFPv4 NEON + option neon-vfpv4 add VFPv4 NEON + option nofp remove ALL_FP + option nosimd remove ALL_SIMD end arch armv7ve begin arch armv7-r @@ -280,10 +280,10 @@ begin arch armv7-r base 7R isa ARMv7r # ARMv7-r uses VFPv3-d16 - option fp add VFPv3 FP_DBL option fp.sp add VFPv3 + option fp add VFPv3 FP_DBL option idiv add bit_adiv - option nofp remove VFPv3 FP_DBL + option nofp remove ALL_FP option noidiv remove bit_adiv end arch armv7-r @@ -305,7 +305,7 @@ begin arch armv7e-m option fp add VFPv4 option fpv5 add FPv5 option fp.dp add FPv5 FP_DBL - option nofp remove FPv5 FP_DBL + option nofp remove ALL_FP end arch armv7e-m begin arch armv8-a @@ -315,9 +315,9 @@ begin arch armv8-a isa ARMv8a option crc add bit_crc32 option simd add FP_ARMv8 NEON - option crypto add FP_ARMv8 NEON CRYPTO - option nofp remove FP_ARMv8 NEON CRYPTO - option nocrypto remove CRYPTO + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP + option nocrypto remove ALL_CRYPTO end arch armv8-a begin arch armv8.1-a @@ -326,9 +326,9 @@ begin arch armv8.1-a base 8A isa ARMv8_1a option simd add FP_ARMv8 NEON - option crypto add FP_ARMv8 NEON CRYPTO - option nofp remove FP_ARMv8 NEON CRYPTO - option nocrypto remove CRYPTO + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP + option nocrypto remove ALL_CRYPTO end arch armv8.1-a begin arch armv8.2-a @@ -336,11 +336,11 @@ begin arch armv8.2-a tune flags CO_PROC base 8A isa ARMv8_2a - option fp16 add bit_fp16 FP_ARMv8 NEON option simd add FP_ARMv8 NEON - option crypto add FP_ARMv8 NEON CRYPTO - option nofp remove bit_fp16 FP_ARMv8 NEON CRYPTO - option nocrypto remove CRYPTO + option fp16 add bit_fp16 FP_ARMv8 NEON + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP + option nocrypto remove ALL_CRYPTO end arch armv8.2-a begin arch armv8-m.base @@ -358,7 +358,7 @@ begin arch armv8-m.main # fp => FPv5-sp-d16; fp.dp => FPv5-d16 option fp add FPv5 option fp.dp add FPv5 FP_DBL - option nofp remove FPv5 + option nofp remove ALL_FP end arch armv8-m.main begin arch iwmmxt @@ -668,6 +668,7 @@ end cpu ep9312 # V5T Architecture Processors +# These used VFPv1 which isn't supported by GCC begin cpu arm10tdmi tune flags LDSCHED architecture armv5t @@ -685,6 +686,8 @@ end cpu arm1020t begin cpu arm9e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm9e @@ -692,6 +695,8 @@ begin cpu arm946e-s cname arm946es tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm946e-s @@ -699,6 +704,8 @@ begin cpu arm966e-s cname arm966es tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm966e-s @@ -706,24 +713,32 @@ begin cpu arm968e-s cname arm968es tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm968e-s begin cpu arm10e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs fastmul end cpu arm10e begin cpu arm1020e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs fastmul end cpu arm1020e begin cpu arm1022e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs fastmul end cpu arm1022e @@ -776,6 +791,8 @@ begin cpu arm926ej-s cname arm926ejs tune flags LDSCHED architecture armv5tej + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm926ej-s @@ -783,6 +800,8 @@ begin cpu arm1026ej-s cname arm1026ejs tune flags LDSCHED architecture armv5tej + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm1026ej-s @@ -901,6 +920,20 @@ begin cpu generic-armv7-a cname genericv7a tune flags LDSCHED architecture armv7-a + fpu vfpv3-d16 + option simd add VFPv3 NEON + option vfpv3 add VFPv3 FP_D32 + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3-fp16 add VFPv3 FP_D32 bit_fp16conv + option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv + option vfpv4 add VFPv4 FP_D32 + option vfpv4-d16 add VFPv4 FP_DBL + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option neon-vfpv4 add VFPv4 NEON + option nofp remove ALL_FP + option nosimd remove ALL_SIMD costs cortex end cpu generic-armv7-a @@ -908,6 +941,9 @@ begin cpu cortex-a5 cname cortexa5 tune flags LDSCHED architecture armv7-a + fpu neon-fp16 + option nosimd remove ALL_SIMD + option nofp remove ALL_FP costs cortex_a5 end cpu cortex-a5 @@ -915,6 +951,9 @@ begin cpu cortex-a7 cname cortexa7 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nosimd remove ALL_SIMD + option nofp remove ALL_FP costs cortex_a7 end cpu cortex-a7 @@ -923,7 +962,7 @@ begin cpu cortex-a8 tune flags LDSCHED architecture armv7-a fpu neon-vfpv3 - option nofp remove NEON VFPv3 + option nofp remove ALL_FP costs cortex_a8 end cpu cortex-a8 @@ -931,9 +970,9 @@ begin cpu cortex-a9 cname cortexa9 tune flags LDSCHED architecture armv7-a - fpu neon-vfpv3 - option nofp remove NEON VFPv3 - option nosimd remove NEON + fpu neon-fp16 + option nofp remove ALL_FP + option nosimd remove ALL_SIMD costs cortex_a9 end cpu cortex-a9 @@ -942,6 +981,8 @@ begin cpu cortex-a12 tune for cortex-a17 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a12 end cpu cortex-a12 @@ -949,6 +990,8 @@ begin cpu cortex-a15 cname cortexa15 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a15 end cpu cortex-a15 @@ -956,6 +999,8 @@ begin cpu cortex-a17 cname cortexa17 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a12 end cpu cortex-a17 @@ -970,22 +1015,26 @@ begin cpu cortex-r4f cname cortexr4f tune flags LDSCHED architecture armv7-r + fpu vfpv3-d16 costs cortex end cpu cortex-r4f begin cpu cortex-r5 cname cortexr5 tune flags LDSCHED - architecture armv7-r - isa bit_adiv + architecture armv7-r+idiv + fpu vfpv3-d16 + option nofp.dp remove FP_DBL + option nofp remove ALL_FP costs cortex end cpu cortex-r5 begin cpu cortex-r7 cname cortexr7 tune flags LDSCHED - architecture armv7-r - isa bit_adiv + architecture armv7-r+idiv + fpu vfpv3-d16 + option nofp remove ALL_FP costs cortex end cpu cortex-r7 @@ -993,8 +1042,9 @@ begin cpu cortex-r8 cname cortexr8 tune for cortex-r7 tune flags LDSCHED - architecture armv7-r - isa bit_adiv + architecture armv7-r+idiv + fpu vfpv3-d16 + option nofp remove ALL_FP costs cortex end cpu cortex-r8 @@ -1003,6 +1053,9 @@ begin cpu cortex-m7 tune flags LDSCHED architecture armv7e-m isa quirk_no_volatile_ce + fpu fpv5-d16 + option nofp.dp remove FP_DBL + option nofp remove ALL_FP costs cortex_m7 end cpu cortex-m7 @@ -1010,6 +1063,8 @@ begin cpu cortex-m4 cname cortexm4 tune flags LDSCHED architecture armv7e-m + fpu fpv4-sp-d16 + option nofp remove ALL_FP costs v7m end cpu cortex-m4 @@ -1034,6 +1089,8 @@ begin cpu cortex-a15.cortex-a7 tune for cortex-a7 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a15 end cpu cortex-a15.cortex-a7 @@ -1042,6 +1099,8 @@ begin cpu cortex-a17.cortex-a7 tune for cortex-a7 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a12 end cpu cortex-a17.cortex-a7 @@ -1052,6 +1111,9 @@ begin cpu cortex-a32 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP costs cortex_a35 end cpu cortex-a32 @@ -1060,6 +1122,9 @@ begin cpu cortex-a35 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP costs cortex_a35 end cpu cortex-a35 @@ -1067,6 +1132,9 @@ begin cpu cortex-a53 cname cortexa53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP costs cortex_a53 end cpu cortex-a53 @@ -1074,6 +1142,8 @@ begin cpu cortex-a57 cname cortexa57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a57 @@ -1082,6 +1152,8 @@ begin cpu cortex-a72 tune for cortex-a57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a72 @@ -1090,6 +1162,8 @@ begin cpu cortex-a73 tune for cortex-a57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a73 end cpu cortex-a73 @@ -1097,6 +1171,8 @@ begin cpu exynos-m1 cname exynosm1 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs exynosm1 end cpu exynos-m1 @@ -1104,6 +1180,8 @@ begin cpu falkor tune for cortex-a57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs qdf24xx end cpu falkor @@ -1111,12 +1189,16 @@ begin cpu qdf24xx tune for cortex-a57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs qdf24xx end cpu qdf24xx begin cpu xgene1 tune flags LDSCHED architecture armv8-a + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs xgene1 end cpu xgene1 @@ -1127,6 +1209,8 @@ begin cpu cortex-a57.cortex-a53 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a57.cortex-a53 @@ -1135,6 +1219,8 @@ begin cpu cortex-a72.cortex-a53 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a72.cortex-a53 @@ -1143,6 +1229,8 @@ begin cpu cortex-a73.cortex-a35 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a73 end cpu cortex-a73.cortex-a35 @@ -1151,6 +1239,8 @@ begin cpu cortex-a73.cortex-a53 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a73 end cpu cortex-a73.cortex-a53 @@ -1167,6 +1257,8 @@ begin cpu cortex-m33 cname cortexm33 tune flags LDSCHED architecture armv8-m.main+dsp + fpu fpv5-sp-d16 + option nofp remove ALL_FP costs v7m end cpu cortex-m33 diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index 7d1e23b..4b5a0f6 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -127,11 +127,25 @@ enum isa_feature #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse +/* List of all cryptographic extensions to stripout if crypto is + disabled. Currently, that's trivial, but we define it anyway for + consistency with the SIMD and FP disable lists. */ +#define ISA_ALL_CRYPTO isa_bit_crypto + +/* List of all SIMD bits to strip out if SIMD is disabled. This does + strip off 32 D-registers, but does not remove support for + double-precision FP. */ +#define ISA_ALL_SIMD isa_bit_fp_d32, isa_bit_neon, ISA_ALL_CRYPTO + /* List of all FPU bits to strip out if -mfpu is used to override the default. isa_bit_fp16 is deliberately missing from this list. */ -#define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, \ - isa_bit_FPv5, isa_bit_FP_ARMv8, isa_bit_neon, isa_bit_fp16conv, \ - isa_bit_fp_dbl, isa_bit_fp_d32, isa_bit_crypto +#define ISA_ALL_FPU_INTERNAL \ + isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5, \ + isa_bit_FP_ARMv8, isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD + +/* Similarly, but including fp16 and other extensions that aren't part of + -mfpu support. */ +#define ISA_ALL_FP isa_bit_fp16, ISA_ALL_FPU_INTERNAL /* Useful combinations. */ #define ISA_VFPv2 isa_bit_VFPv2 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a1615bf..afb4a4b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3440,7 +3440,8 @@ arm_configure_build_target (struct arm_build_target *target, static void arm_option_override (void) { - static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit }; + static const enum isa_feature fpu_bitlist[] + = { ISA_ALL_FPU_INTERNAL, isa_nobit }; static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit}; cl_target_option opts;

[06/30,arm] Add default FPUs for CPUs.

Commit Message

Patch