From patchwork Tue May 12 20:30:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 48410 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f197.google.com (mail-lb0-f197.google.com [209.85.217.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D0F802121F for ; Tue, 12 May 2015 20:34:17 +0000 (UTC) Received: by lbos2 with SMTP id s2sf4390819lbo.2 for ; Tue, 12 May 2015 13:34:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:mailing-list :precedence:list-id:list-unsubscribe:list-archive:list-post :list-help:sender:delivered-to:from:to:subject:date:message-id :in-reply-to:references:x-original-sender :x-original-authentication-results; bh=hpxSA0l+sIIMCipljKpHftyPkXHAabish4I3J2mrDOI=; b=HA4rxjh24Dc6oUjKx32N6i2GG4qcK1H6kvZjbVAaP+BdUp/m/L6MNSirslHsea34h1 d8wblGiNrUEtG24M8cj8DHGgV/VPlzKAqyMNNJIzDnYlLQla9Z0up+C9kvIr8jisQl0a GqNIlOgnWLCJYysow10PlhsAoSWNVh2hpsKtvuLDwCGJKKAv0aXR8whcAY19IvPzcnzS yzrdEiGojf1Ng3O3r5LjoTaRqkkDz2P8WDY3JzmeBwQPzmIF1kI96w17a5iPGvUpvn5O VamK8Ootdc7jybGqg3eBPu6PeocNEG8zM2g58ul7VECu4NOEU2o0SSvrPqsM8rQoelsP +iLQ== X-Gm-Message-State: ALoCoQle5qcf3NT6+JTc0S8PJHnG2aWfRfGz+wzGhj5cclsoo31vrWY7VtzCrKuqj2RqKbxD1rd9 X-Received: by 10.194.249.1 with SMTP id yq1mr11757807wjc.2.1431462856619; Tue, 12 May 2015 13:34:16 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.116.7 with SMTP id js7ls83461lab.34.gmail; Tue, 12 May 2015 13:34:16 -0700 (PDT) X-Received: by 10.152.204.40 with SMTP id kv8mr13178320lac.113.1431462856312; Tue, 12 May 2015 13:34:16 -0700 (PDT) Received: from mail-lb0-x231.google.com (mail-lb0-x231.google.com. [2a00:1450:4010:c04::231]) by mx.google.com with ESMTPS id mq2si11011932lbb.91.2015.05.12.13.34.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 May 2015 13:34:16 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::231 as permitted sender) client-ip=2a00:1450:4010:c04::231; Received: by lbbuc2 with SMTP id uc2so14879814lbb.2 for ; Tue, 12 May 2015 13:34:16 -0700 (PDT) X-Received: by 10.152.4.137 with SMTP id k9mr522835lak.29.1431462856168; Tue, 12 May 2015 13:34:16 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp137496lbb; Tue, 12 May 2015 13:34:14 -0700 (PDT) X-Received: by 10.66.231.42 with SMTP id td10mr30905037pac.98.1431462853991; Tue, 12 May 2015 13:34:13 -0700 (PDT) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id ns8si16381460pbc.246.2015.05.12.13.34.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 May 2015 13:34:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-397718-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 76754 invoked by alias); 12 May 2015 20:31:29 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 76653 invoked by uid 89); 12 May 2015 20:31:28 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f174.google.com Received: from mail-wi0-f174.google.com (HELO mail-wi0-f174.google.com) (209.85.212.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 12 May 2015 20:31:26 +0000 Received: by wicnf17 with SMTP id nf17so30759662wic.1 for ; Tue, 12 May 2015 13:31:23 -0700 (PDT) X-Received: by 10.194.48.48 with SMTP id i16mr34172926wjn.40.1431462683007; Tue, 12 May 2015 13:31:23 -0700 (PDT) Received: from babel.clyon.hd.free.fr (vig38-2-82-225-222-175.fbx.proxad.net. [82.225.222.175]) by mx.google.com with ESMTPSA id u9sm24921095wju.44.2015.05.12.13.31.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 May 2015 13:31:22 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [Patch ARM-AArch64/testsuite Neon intrinsics 11/13] Add vqshlu_n tests. Date: Tue, 12 May 2015 22:30:59 +0200 Message-Id: <1431462661-27247-12-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1431462661-27247-1-git-send-email-christophe.lyon@linaro.org> References: <1431462661-27247-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::231 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshlu_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshlu_n.c new file mode 100644 index 0000000..a6710ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqshlu_n.c @@ -0,0 +1,263 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected values of cumulative_saturation flag with negative + input. */ +int VECT_VAR(expected_cumulative_sat_neg,int,8,8) = 1; +int VECT_VAR(expected_cumulative_sat_neg,int,16,4) = 1; +int VECT_VAR(expected_cumulative_sat_neg,int,32,2) = 1; +int VECT_VAR(expected_cumulative_sat_neg,int,64,1) = 1; +int VECT_VAR(expected_cumulative_sat_neg,int,8,16) = 1; +int VECT_VAR(expected_cumulative_sat_neg,int,16,8) = 1; +int VECT_VAR(expected_cumulative_sat_neg,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat_neg,int,64,2) = 1; + +/* Expected results with negative input. */ +VECT_VAR_DECL(expected_neg,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL(expected_neg,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL(expected_neg,uint,32,2) [] = { 0x0, 0x0 }; +VECT_VAR_DECL(expected_neg,uint,64,1) [] = { 0x0 }; +VECT_VAR_DECL(expected_neg,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL(expected_neg,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL(expected_neg,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; +VECT_VAR_DECL(expected_neg,uint,64,2) [] = { 0x0, 0x0 }; + +/* Expected values of cumulative_saturation flag with shift by 1. */ +int VECT_VAR(expected_cumulative_sat_sh1,int,8,8) = 0; +int VECT_VAR(expected_cumulative_sat_sh1,int,16,4) = 0; +int VECT_VAR(expected_cumulative_sat_sh1,int,32,2) = 0; +int VECT_VAR(expected_cumulative_sat_sh1,int,64,1) = 0; +int VECT_VAR(expected_cumulative_sat_sh1,int,8,16) = 0; +int VECT_VAR(expected_cumulative_sat_sh1,int,16,8) = 0; +int VECT_VAR(expected_cumulative_sat_sh1,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat_sh1,int,64,2) = 0; + +/* Expected results with shift by 1. */ +VECT_VAR_DECL(expected_sh1,uint,8,8) [] = { 0xfe, 0xfe, 0xfe, 0xfe, + 0xfe, 0xfe, 0xfe, 0xfe }; +VECT_VAR_DECL(expected_sh1,uint,16,4) [] = { 0xfffe, 0xfffe, 0xfffe, 0xfffe }; +VECT_VAR_DECL(expected_sh1,uint,32,2) [] = { 0xfffffffe, 0xfffffffe }; +VECT_VAR_DECL(expected_sh1,uint,64,1) [] = { 0xfffffffffffffffe }; +VECT_VAR_DECL(expected_sh1,uint,8,16) [] = { 0xfe, 0xfe, 0xfe, 0xfe, + 0xfe, 0xfe, 0xfe, 0xfe, + 0xfe, 0xfe, 0xfe, 0xfe, + 0xfe, 0xfe, 0xfe, 0xfe }; +VECT_VAR_DECL(expected_sh1,uint,16,8) [] = { 0xfffe, 0xfffe, 0xfffe, 0xfffe, + 0xfffe, 0xfffe, 0xfffe, 0xfffe }; +VECT_VAR_DECL(expected_sh1,uint,32,4) [] = { 0xfffffffe, 0xfffffffe, + 0xfffffffe, 0xfffffffe }; +VECT_VAR_DECL(expected_sh1,uint,64,2) [] = { 0xfffffffffffffffe, + 0xfffffffffffffffe }; + +/* Expected values of cumulative_saturation flag with shift by 2. */ +int VECT_VAR(expected_cumulative_sat_sh2,int,8,8) = 1; +int VECT_VAR(expected_cumulative_sat_sh2,int,16,4) = 1; +int VECT_VAR(expected_cumulative_sat_sh2,int,32,2) = 1; +int VECT_VAR(expected_cumulative_sat_sh2,int,64,1) = 1; +int VECT_VAR(expected_cumulative_sat_sh2,int,8,16) = 1; +int VECT_VAR(expected_cumulative_sat_sh2,int,16,8) = 1; +int VECT_VAR(expected_cumulative_sat_sh2,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat_sh2,int,64,2) = 1; + +/* Expected results with shift by 2. */ +VECT_VAR_DECL(expected_sh2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(expected_sh2,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL(expected_sh2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; +VECT_VAR_DECL(expected_sh2,uint,64,1) [] = { 0xffffffffffffffff }; +VECT_VAR_DECL(expected_sh2,uint,8,16) [] = { 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(expected_sh2,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL(expected_sh2,uint,32,4) [] = { 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff }; +VECT_VAR_DECL(expected_sh2,uint,64,2) [] = { 0xffffffffffffffff, + 0xffffffffffffffff }; + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,8,8) = 0; +int VECT_VAR(expected_cumulative_sat,int,16,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,32,2) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,1) = 0; +int VECT_VAR(expected_cumulative_sat,int,8,16) = 0; +int VECT_VAR(expected_cumulative_sat,int,16,8) = 0; +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0; + +/* Expected results. */ +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x8, 0x8, 0x8, 0x8 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x18, 0x18 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x40 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xa0, 0xa0, 0xa0, 0xa0, + 0xa0, 0xa0, 0xa0, 0xa0, + 0xa0, 0xa0, 0xa0, 0xa0, + 0xa0, 0xa0, 0xa0, 0xa0 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x180, 0x180, 0x180, 0x180, + 0x180, 0x180, 0x180, 0x180 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x380, 0x380, 0x380, 0x380 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x800, 0x800 }; + + +#define INSN vqshlu +#define TEST_MSG "VQSHLU_N/VQSHLUQ_N" + +#define FNNAME1(NAME) void exec_ ## NAME ## _n(void) +#define FNNAME(NAME) FNNAME1(NAME) + +FNNAME (INSN) +{ + /* Basic test: v2=vqshlu_n(v1,v), then store the result. */ +#define TEST_VQSHLU_N2(INSN, Q, T1, T2, T3, T4, W, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \ + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T3, W, N)); \ + VECT_VAR(vector_res, T3, W, N) = \ + INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \ + V); \ + vst1##Q##_##T4##W(VECT_VAR(result, T3, W, N), \ + VECT_VAR(vector_res, T3, W, N)); \ + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT) + + /* Two auxliary macros are necessary to expand INSN */ +#define TEST_VQSHLU_N1(INSN, Q, T1, T2, T3, T4, W, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \ + TEST_VQSHLU_N2(INSN, Q, T1, T2, T3, T4, W, N, V, EXPECTED_CUMULATIVE_SAT, CMT) + +#define TEST_VQSHLU_N(Q, T1, T2, T3, T4, W, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \ + TEST_VQSHLU_N1(INSN, Q, T1, T2, T3, T4, W, N, V, EXPECTED_CUMULATIVE_SAT, CMT) + + + DECL_VARIABLE_ALL_VARIANTS(vector); + DECL_VARIABLE_ALL_VARIANTS(vector_res); + + clean_results (); + + /* Fill input vector with negative values, to check saturation on + limits. */ + VDUP(vector, , int, s, 8, 8, -1); + VDUP(vector, , int, s, 16, 4, -2); + VDUP(vector, , int, s, 32, 2, -3); + VDUP(vector, , int, s, 64, 1, -4); + VDUP(vector, q, int, s, 8, 16, -1); + VDUP(vector, q, int, s, 16, 8, -2); + VDUP(vector, q, int, s, 32, 4, -3); + VDUP(vector, q, int, s, 64, 2, -4); + + /* Choose shift amount arbitrarily. */ +#define CMT " (negative input)" + TEST_VQSHLU_N(, int, s, uint, u, 8, 8, 2, expected_cumulative_sat_neg, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 16, 4, 1, expected_cumulative_sat_neg, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 32, 2, 1, expected_cumulative_sat_neg, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 64, 1, 2, expected_cumulative_sat_neg, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 8, 16, 2, expected_cumulative_sat_neg, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 16, 8, 1, expected_cumulative_sat_neg, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 32, 4, 1, expected_cumulative_sat_neg, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 64, 2, 2, expected_cumulative_sat_neg, CMT); + + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_neg, CMT); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_neg, CMT); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_neg, CMT); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_neg, CMT); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_neg, CMT); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_neg, CMT); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_neg, CMT); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_neg, CMT); + + + /* Fill input vector with max value, to check saturation on + limits. */ + VDUP(vector, , int, s, 8, 8, 0x7F); + VDUP(vector, , int, s, 16, 4, 0x7FFF); + VDUP(vector, , int, s, 32, 2, 0x7FFFFFFF); + VDUP(vector, , int, s, 64, 1, 0x7FFFFFFFFFFFFFFFLL); + VDUP(vector, q, int, s, 8, 16, 0x7F); + VDUP(vector, q, int, s, 16, 8, 0x7FFF); + VDUP(vector, q, int, s, 32, 4, 0x7FFFFFFF); + VDUP(vector, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFULL); + + /* shift by 1. */ +#undef CMT +#define CMT " (shift by 1)" + TEST_VQSHLU_N(, int, s, uint, u, 8, 8, 1, expected_cumulative_sat_sh1, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 16, 4, 1, expected_cumulative_sat_sh1, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 32, 2, 1, expected_cumulative_sat_sh1, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 64, 1, 1, expected_cumulative_sat_sh1, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 8, 16, 1, expected_cumulative_sat_sh1, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 16, 8, 1, expected_cumulative_sat_sh1, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 32, 4, 1, expected_cumulative_sat_sh1, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 64, 2, 1, expected_cumulative_sat_sh1, CMT); + + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_sh1, CMT); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_sh1, CMT); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_sh1, CMT); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_sh1, CMT); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_sh1, CMT); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_sh1, CMT); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_sh1, CMT); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_sh1, CMT); + + /* shift by 2 to force saturation. */ +#undef CMT +#define CMT " (shift by 2)" + TEST_VQSHLU_N(, int, s, uint, u, 8, 8, 2, expected_cumulative_sat_sh2, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 16, 4, 2, expected_cumulative_sat_sh2, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 32, 2, 2, expected_cumulative_sat_sh2, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 64, 1, 2, expected_cumulative_sat_sh2, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 8, 16, 2, expected_cumulative_sat_sh2, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 16, 8, 2, expected_cumulative_sat_sh2, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 32, 4, 2, expected_cumulative_sat_sh2, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 64, 2, 2, expected_cumulative_sat_sh2, CMT); + + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_sh2, CMT); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_sh2, CMT); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_sh2, CMT); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_sh2, CMT); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_sh2, CMT); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_sh2, CMT); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_sh2, CMT); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_sh2, CMT); + + + /* Fill input vector with positive values, to check normal case. */ + VDUP(vector, , int, s, 8, 8, 1); + VDUP(vector, , int, s, 16, 4, 2); + VDUP(vector, , int, s, 32, 2, 3); + VDUP(vector, , int, s, 64, 1, 4); + VDUP(vector, q, int, s, 8, 16, 5); + VDUP(vector, q, int, s, 16, 8, 6); + VDUP(vector, q, int, s, 32, 4, 7); + VDUP(vector, q, int, s, 64, 2, 8); + + /* Arbitrary shift amount. */ +#undef CMT +#define CMT "" + TEST_VQSHLU_N(, int, s, uint, u, 8, 8, 1, expected_cumulative_sat, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 16, 4, 2, expected_cumulative_sat, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 32, 2, 3, expected_cumulative_sat, CMT); + TEST_VQSHLU_N(, int, s, uint, u, 64, 1, 4, expected_cumulative_sat, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 8, 16, 5, expected_cumulative_sat, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 16, 8, 6, expected_cumulative_sat, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 32, 4, 7, expected_cumulative_sat, CMT); + TEST_VQSHLU_N(q, int, s, uint, u, 64, 2, 8, expected_cumulative_sat, CMT); + + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT); + CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, CMT); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, CMT); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, CMT); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, CMT); +} + +int main (void) +{ + exec_vqshlu_n (); + return 0; +}