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helo=nebula.arm.com; Received: from nebula.arm.com (217.140.96.140) by DB5EUR03FT034.mail.protection.outlook.com (10.152.20.87) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.1.1385.11 via Frontend Transport; Thu, 31 Aug 2017 16:04:01 +0000 Received: from e107456-lin.cambridge.arm.com (10.1.2.79) by mail.arm.com (10.1.105.66) with Microsoft SMTP Server id 14.3.294.0; Thu, 31 Aug 2017 17:03:58 +0100 From: James Greenhalgh To: CC: , , Subject: [AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge Date: Thu, 31 Aug 2017 17:03:54 +0100 Message-ID: <1504195434-26009-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:217.140.96.140; IPV:CAL; SCL:-1; CTRY:GB; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(2980300002)(438002)(189002)(377424004)(199003)(26826003)(568964002)(189998001)(478600001)(50226002)(626005)(36756003)(4326008)(2476003)(72206003)(2906002)(84326002)(5890100001)(8936002)(110136004)(86362001)(5000100001)(4610100001)(2351001)(8676002)(77096006)(5660300001)(54906002)(33646002)(104016004)(50986999)(106466001)(246002)(6666003)(305945005)(512874002)(6916009)(356003); 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Ip=[217.140.96.140]; Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR0801MB1527 X-IsSubscribed: yes Hi, The MLA by-element instructions have the same restriction as other by-element instructions whereby the forms operating on vectors of 16-bit integer data may only use registers v0-v15. We have an iterator for that, applied to the other patterns generating this instruction, so use that. Bootstrap and test OK, Applied as r251568. Thanks, James --- 2017-08-31 James Greenhalgh * config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge): Fix register constraint for by-element operand. (aarch64_mls_elt_merge): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bf2db02..051d2a9 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1072,7 +1072,7 @@ [(set (match_operand:VDQHS 0 "register_operand" "=w") (plus:VDQHS (mult:VDQHS (vec_duplicate:VDQHS - (match_operand: 1 "register_operand" "w")) + (match_operand: 1 "register_operand" "")) (match_operand:VDQHS 2 "register_operand" "w")) (match_operand:VDQHS 3 "register_operand" "0")))] "TARGET_SIMD" @@ -1132,7 +1132,7 @@ (minus:VDQHS (match_operand:VDQHS 1 "register_operand" "0") (mult:VDQHS (vec_duplicate:VDQHS - (match_operand: 2 "register_operand" "w")) + (match_operand: 2 "register_operand" "")) (match_operand:VDQHS 3 "register_operand" "w"))))] "TARGET_SIMD" "mls\t%0., %3., %2.[0]"