From patchwork Thu Dec 15 16:07:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 88192 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp882752qgi; Thu, 15 Dec 2016 08:11:18 -0800 (PST) X-Received: by 10.84.176.131 with SMTP id v3mr4017862plb.51.1481818278667; Thu, 15 Dec 2016 08:11:18 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 3si3153206plr.96.2016.12.15.08.11.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Dec 2016 08:11:18 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444534-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444534-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444534-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=a3AM1GxEIpRUXqoJN9+YnV/af1uo2 H4rM7m3If2EjlU8sMJs87md4YQ02t6+SKg6C3S9h79H273pRWYTNJKPWTrOQ05x5 yHxKqHllcNK1okH3dwNUnlqdMp++8z2dHU5/qGYz+ELd/MRZi91R8A6t3Y+DWfbF 7NEvD2FyL1nO9E= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=zYRB18Jez5SasHrKEhZSnFhu+x0=; b=C2q Ll8UJmR5L2sn5dhQUUkA0OEav/bht+eiAZk/xYzs3h/6mxKMnwuNHKOCusOZ0eDW 68d0Ofo8PqxpZYjixBp12cG//oqv+YHa3maXPXZdR1HuSWMqHzotJV8kAEH+smSr 1Q+Ksrf4wSahNGw+xYmA5K1SiShrwXsakYQFOYTw= Received: (qmail 44868 invoked by alias); 15 Dec 2016 16:08:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 44818 invoked by uid 89); 15 Dec 2016 16:08:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:08:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AA9131516; Thu, 15 Dec 2016 08:08:00 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5C0CC3F445 for ; Thu, 15 Dec 2016 08:08:00 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 20/21] [arm] Remove FEATURES field from FPU descriptions. To: gcc-patches@gcc.gnu.org References: Message-ID: <286d648a-e1fb-4a69-809a-dfee2c93cd6f@arm.com> Date: Thu, 15 Dec 2016 16:07:59 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: Now that everything uses the new ISA features, we can remove the FEATURES field from the FPU descriptions, along with all the macros and definitions associated with it. * arm-fpus.def (ARM_FPU): Remove features field from all definitions. * arm.h (arm_fpu_feature_set): Delete typedef. (FPU_FL_NONE): Delete. (FPU_FL_NEON): Delete. (FPU_FL_FP16): Delete. (FPU_FL_CRYPTO): Delete. (FPU_FL_DBL): Delete. (FPU_FL_D32): Delete. (FPU_FL_VFPv2): Delete. (FPU_FL_VFPv3): Delete. (FPU_FL_VFPv4): Delete. (FPU_FL_VFPv5): Delete. (FPU_FL_AMRv8): Delete. (FPU_VFPv2): Delete. (FPU_VFPv3): Delete. (FPU_VFPv4): Delete. (FPU_VFPv5): Delete. (FPU_ARMv8): Delete. (FPU_DBL): Delete. (FPU_D32): Delete. (FPU_NEON): Delete. (FPU_CRYPTO): Delete. (FPU_FP16): Delete. (arm_fpu_desc): Delete features field. * arm.c (all_fpus): Don't initialize feature field. --- gcc/config/arm/arm-fpus.def | 44 ++++++++++++++++++++++---------------------- gcc/config/arm/arm.c | 4 ++-- gcc/config/arm/arm.h | 34 ---------------------------------- 3 files changed, 24 insertions(+), 58 deletions(-) diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index 1be718f..ae8197d 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -19,31 +19,31 @@ /* Before using #include to read this file, define a macro: - ARM_FPU(NAME, ISA, FEATURES) + ARM_FPU(NAME, ISA) The arguments are the fields of struct arm_fpu_desc. genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL) -ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL) -ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32) -ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_D32 | FPU_FP16) -ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL), FPU_VFPv3 | FPU_DBL) -ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_DBL | FPU_FP16) -ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3), FPU_VFPv3) -ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_FP16) -ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON) -ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON) -ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_NEON | FPU_FP16) -ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32), FPU_VFPv4 | FPU_D32 | FPU_FP16) -ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON), FPU_VFPv4 | FPU_NEON | FPU_FP16) -ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL), FPU_VFPv4 | FPU_DBL | FPU_FP16) -ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4), FPU_VFPv4 | FPU_FP16) -ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5), FPU_VFPv5 | FPU_FP16) -ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL), FPU_VFPv5 | FPU_DBL | FPU_FP16) -ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32), FPU_ARMv8 | FPU_D32 | FPU_FP16) -ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON), FPU_ARMv8 | FPU_NEON | FPU_FP16) -ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO), FPU_ARMv8 | FPU_CRYPTO | FPU_FP16) +ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3)) +ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) +ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) +ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON)) +ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4)) +ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5)) +ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON)) +ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO)) /* Compatibility aliases. */ -ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32) +ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 1d3bb89..522989d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2328,8 +2328,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__"; const struct arm_fpu_desc all_fpus[] = { -#define ARM_FPU(NAME, ISA, FEATURES) \ - { NAME, {ISA isa_nobit}, FEATURES }, +#define ARM_FPU(NAME, ISA) \ + { NAME, {ISA isa_nobit} }, #include "arm-fpus.def" #undef ARM_FPU }; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 17f030b..4582d2e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -326,44 +326,10 @@ extern tree arm_fp16_type_node; {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, -/* FPU feature sets. */ - -typedef unsigned long arm_fpu_feature_set; - -/* Test for an FPU feature. */ -#define ARM_FPU_FSET_HAS(S,F) (((S) & (F)) == (F)) - -/* FPU Features. */ -#define FPU_FL_NONE (0u) -#define FPU_FL_NEON (1u << 0) /* NEON instructions. */ -#define FPU_FL_FP16 (1u << 1) /* Half-precision. */ -#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */ -#define FPU_FL_DBL (1u << 3) /* Has double precision. */ -#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */ -#define FPU_FL_VFPv2 (1u << 5) /* Has VFPv2 features. */ -#define FPU_FL_VFPv3 (1u << 6) /* Has VFPv3 extensions. */ -#define FPU_FL_VFPv4 (1u << 7) /* Has VFPv4 extensions. */ -#define FPU_FL_VFPv5 (1u << 8) /* Has VFPv5 extensions. */ -#define FPU_FL_ARMv8 (1u << 9) /* Has ARMv8 extensions to VFP. */ - -/* Some useful combinations. */ -#define FPU_VFPv2 (FPU_FL_VFPv2) -#define FPU_VFPv3 (FPU_VFPv2 | FPU_FL_VFPv3) -#define FPU_VFPv4 (FPU_VFPv3 | FPU_FL_VFPv4) -#define FPU_VFPv5 (FPU_VFPv4 | FPU_FL_VFPv5) -#define FPU_ARMv8 (FPU_VFPv5 | FPU_FL_ARMv8) - -#define FPU_DBL (FPU_FL_DBL) -#define FPU_D32 (FPU_DBL | FPU_FL_D32) -#define FPU_NEON (FPU_D32 | FPU_FL_NEON) -#define FPU_CRYPTO (FPU_NEON | FPU_FL_CRYPTO) -#define FPU_FP16 (FPU_FL_FP16) - extern const struct arm_fpu_desc { const char *name; enum isa_feature isa_bits[isa_num_bits]; - arm_fpu_feature_set features; } all_fpus[]; /* Which floating point hardware to schedule for. */