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[209.132.180.131]) by mx.google.com with ESMTPS id r86si11506328pfk.297.2016.11.03.13.57.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Nov 2016 13:57:12 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-440388-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-440388-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-440388-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=w4muxlt+Quy7pcve nm7d6OYQyzFFSGH8gqto/qQhY+b34QhxsQvWsX1m1Vdnd/fx1odSiKNAqOQDi2P3 cqUze4DdobyCQrLvBQ6uQpzDef4Lqm5j+IGtf67xBwxO23sEGlCRRx67Khs5nfEP y2DGTEbXuPFWMlP2/aT1J7tETHE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=y/2bw0eG2TQvdpcI8KBIfO EEQ0E=; b=MAgHQE6yGaD7dDqX3zoEFlfXtwsIrTGqycQPnxdUtPMQRfoF+RrY2f Y0BgVP+I5Tlt15ONI+7OO/3RGEh8KirWjUlS8HPub8kekDOOnU/Stk69Ang44sp6 brgPZzZ3T7YN4KYV3fofmzq822ZDliXympkmBrcOzgb9QY8/pYd6w= Received: (qmail 125130 invoked by alias); 3 Nov 2016 20:56:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 125117 invoked by uid 89); 3 Nov 2016 20:56:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=no version=3.3.2 spammy=subreg, 1046, 104, 6, moreover X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 03 Nov 2016 20:56:45 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 4F5AD81330 for ; Thu, 3 Nov 2016 21:56:42 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7EE-iTKruwYz for ; Thu, 3 Nov 2016 21:56:42 +0100 (CET) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 13CAD8132E for ; Thu, 3 Nov 2016 21:56:42 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [patch] Clean up WORD_REGISTER_OPERATIONS & LOAD_EXTEND_OP tests Date: Thu, 03 Nov 2016 21:56:41 +0100 Message-ID: <2944236.JHK1hthVPr@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-48-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 Hi, WORD_REGISTER_OPERATIONS and LOAD_EXTEND_OP are partially used directly as preprocessor macros and partially tested in the code. This patch brings a bit of consistency into this by converting the remaining macro cases. Tested on SPARC/Solaris and x86-64/Linux, OK for the mainline? 2016-11-03 Eric Botcazou * defaults.h (LOAD_EXTEND_OP): Define if not already defined. * combine.c (LOAD_EXTEND_OP): Delete. (simplify_comparison): Fix comment on LOAD_EXTEND_OP. * cse.c (LOAD_EXTEND_OP): Delete. * fold-const.c (LOAD_EXTEND_OP): Likewise. * fwprop.c (free_load_extend): Remove #ifdef LOAD_EXTEND_OP/#endif. * postreload.c (LOAD_EXTEND_OP): Delete. * reload.c (push_reload): Remove #ifdef LOAD_EXTEND_OP/#endif. Convert conditional compilation based on WORD_REGISTER_OPERATIONS. (find_reloads): Likewise. * reload1.c (eliminate_regs_1): Likewise. * rtlanal.c (nonzero_bits1): Remove #ifdef LOAD_EXTEND_OP/#endif. (num_sign_bit_copies1): Likewise. -- Eric Botcazou Index: combine.c =================================================================== --- combine.c (revision 241808) +++ combine.c (working copy) @@ -104,10 +104,6 @@ along with GCC; see the file COPYING3. #include "rtl-iter.h" #include "print-rtl.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - /* Number of attempts to combine instructions in this function. */ static int combine_attempts; @@ -12462,14 +12458,14 @@ simplify_comparison (enum rtx_code code, care bits and we can assume they have any convenient value. So making the transformation is safe. - 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. + 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN. In this case the upper bits of op0 are undefined. We should not make the simplification in that case as we do not know the contents of those bits. - 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not - UNKNOWN. In that case we know those bits are zeros or ones. We must - also be sure that they are the same as the upper bits of op1. + 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN. + In that case we know those bits are zeros or ones. We must also be + sure that they are the same as the upper bits of op1. We can never remove a SUBREG for a non-equality comparison because the sign bit is in a different place in the underlying object. */ Index: cse.c =================================================================== --- cse.c (revision 241808) +++ cse.c (working copy) @@ -43,10 +43,6 @@ along with GCC; see the file COPYING3. #include "dbgcnt.h" #include "rtl-iter.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - /* The basic idea of common subexpression elimination is to go through the code, keeping a record of expressions that would have the same value at the current scan point, and replacing Index: defaults.h =================================================================== --- defaults.h (revision 241808) +++ defaults.h (working copy) @@ -1259,6 +1259,10 @@ see the files COPYING3 and COPYING.RUNTI #define WORD_REGISTER_OPERATIONS 0 #endif +#ifndef LOAD_EXTEND_OP +#define LOAD_EXTEND_OP(M) UNKNOWN +#endif + #ifndef CONSTANT_ALIGNMENT #define CONSTANT_ALIGNMENT(EXP, ALIGN) ALIGN #endif Index: fold-const.c =================================================================== --- fold-const.c (revision 241808) +++ fold-const.c (working copy) @@ -80,10 +80,6 @@ along with GCC; see the file COPYING3. #include "tree-ssanames.h" #include "selftest.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - /* Nonzero if we are folding constants inside an initializer; zero otherwise. */ int folding_initializer = 0; Index: fwprop.c =================================================================== --- fwprop.c (revision 241808) +++ fwprop.c (working copy) @@ -1051,9 +1051,7 @@ free_load_extend (rtx src, rtx_insn *ins df_ref def, use; reg = XEXP (src, 0); -#ifdef LOAD_EXTEND_OP if (LOAD_EXTEND_OP (GET_MODE (reg)) != GET_CODE (src)) -#endif return false; FOR_EACH_INSN_USE (use, insn) Index: postreload.c =================================================================== --- postreload.c (revision 241808) +++ postreload.c (working copy) @@ -41,10 +41,6 @@ along with GCC; see the file COPYING3. #include "tree-pass.h" #include "dbgcnt.h" -#ifndef LOAD_EXTEND_OP -#define LOAD_EXTEND_OP(M) UNKNOWN -#endif - static int reload_cse_noop_set_p (rtx); static bool reload_cse_simplify (rtx_insn *, rtx); static void reload_cse_regs_1 (void); Index: reload.c =================================================================== --- reload.c (revision 241808) +++ reload.c (working copy) @@ -1064,7 +1064,6 @@ push_reload (rtx in, rtx out, rtx *inloc || MEM_P (SUBREG_REG (in))) && ((GET_MODE_PRECISION (inmode) > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) -#ifdef LOAD_EXTEND_OP || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) <= UNITS_PER_WORD) @@ -1072,15 +1071,12 @@ push_reload (rtx in, rtx out, rtx *inloc > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN) -#endif -#if WORD_REGISTER_OPERATIONS - || ((GET_MODE_PRECISION (inmode) - < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) + || (WORD_REGISTER_OPERATIONS + && (GET_MODE_PRECISION (inmode) + < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in)))) && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1) - / UNITS_PER_WORD))) -#endif - )) + / UNITS_PER_WORD))))) || (REG_P (SUBREG_REG (in)) && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER /* The case where out is nonzero @@ -1111,13 +1107,14 @@ push_reload (rtx in, rtx out, rtx *inloc #endif inloc = &SUBREG_REG (in); in = *inloc; -#if ! defined (LOAD_EXTEND_OP) + if (!WORD_REGISTER_OPERATIONS + && LOAD_EXTEND_OP (GET_MODE (in)) == UNKNOWN && MEM_P (in)) /* This is supposed to happen only for paradoxical subregs made by combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode)); -#endif + inmode = GET_MODE (in); } @@ -1175,14 +1172,12 @@ push_reload (rtx in, rtx out, rtx *inloc || MEM_P (SUBREG_REG (out))) && ((GET_MODE_PRECISION (outmode) > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) -#if WORD_REGISTER_OPERATIONS - || ((GET_MODE_PRECISION (outmode) - < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) + || (WORD_REGISTER_OPERATIONS + && (GET_MODE_PRECISION (outmode) + < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out)))) && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1) - / UNITS_PER_WORD))) -#endif - )) + / UNITS_PER_WORD))))) || (REG_P (SUBREG_REG (out)) && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER /* The case of a word mode subreg @@ -3139,24 +3134,21 @@ find_reloads (rtx_insn *insn, int replac || ((MEM_P (operand) || (REG_P (operand) && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) -#if !WORD_REGISTER_OPERATIONS - && (((GET_MODE_BITSIZE (GET_MODE (operand)) - < BIGGEST_ALIGNMENT) - && (GET_MODE_SIZE (operand_mode[i]) - > GET_MODE_SIZE (GET_MODE (operand)))) + && (WORD_REGISTER_OPERATIONS + || ((GET_MODE_BITSIZE (GET_MODE (operand)) + < BIGGEST_ALIGNMENT) + && (GET_MODE_SIZE (operand_mode[i]) + > GET_MODE_SIZE (GET_MODE (operand)))) || BYTES_BIG_ENDIAN -#ifdef LOAD_EXTEND_OP - || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD + || ((GET_MODE_SIZE (operand_mode[i]) + <= UNITS_PER_WORD) && (GET_MODE_SIZE (GET_MODE (operand)) <= UNITS_PER_WORD) && (GET_MODE_SIZE (operand_mode[i]) > GET_MODE_SIZE (GET_MODE (operand))) && INTEGRAL_MODE_P (GET_MODE (operand)) - && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN) -#endif - ) -#endif - ) + && LOAD_EXTEND_OP (GET_MODE (operand)) + != UNKNOWN))) ) force_reload = 1; } Index: reload1.c =================================================================== --- reload1.c (revision 241808) +++ reload1.c (working copy) @@ -2819,18 +2819,16 @@ eliminate_regs_1 (rtx x, machine_mode me if (MEM_P (new_rtx) && ((x_size < new_size -#if WORD_REGISTER_OPERATIONS - /* On these machines, combine can create rtl of the form + /* On RISC machines, combine can create rtl of the form (set (subreg:m1 (reg:m2 R) 0) ...) where m1 < m2, and expects something interesting to happen to the entire word. Moreover, it will use the (reg:m2 R) later, expecting all bits to be preserved. So if the number of words is the same, preserve the subreg so that push_reload can see it. */ - && ! ((x_size - 1) / UNITS_PER_WORD - == (new_size -1 ) / UNITS_PER_WORD) -#endif - ) + && !(WORD_REGISTER_OPERATIONS + && (x_size - 1) / UNITS_PER_WORD + == (new_size -1 ) / UNITS_PER_WORD)) || x_size == new_size) ) return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x)); Index: rtlanal.c =================================================================== --- rtlanal.c (revision 241820) +++ rtlanal.c (working copy) @@ -4361,13 +4361,11 @@ nonzero_bits1 (const_rtx x, machine_mode return UINTVAL (x); case MEM: -#ifdef LOAD_EXTEND_OP /* In many, if not most, RISC machines, reading a byte from memory zeros the rest of the register. Noticing that fact saves a lot of extra zero-extends. */ if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) nonzero &= GET_MODE_MASK (GET_MODE (x)); -#endif break; case EQ: case NE: @@ -4567,7 +4565,6 @@ nonzero_bits1 (const_rtx x, machine_mode nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#ifdef LOAD_EXTEND_OP /* On many CISC machines, accessing an object in a wider mode causes the high-order bits to become undefined. So they are not known to be zero. */ @@ -4578,7 +4575,6 @@ nonzero_bits1 (const_rtx x, machine_mode ? val_signbit_known_set_p (inner_mode, nonzero) : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) || !MEM_P (SUBREG_REG (x)))) -#endif { if (GET_MODE_PRECISION (GET_MODE (x)) > GET_MODE_PRECISION (inner_mode)) @@ -4824,10 +4820,7 @@ num_sign_bit_copies1 (const_rtx x, machi than a word and loads of that size don't sign extend, we can say nothing about the high order bits. */ if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD -#ifdef LOAD_EXTEND_OP - && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND -#endif - ) + && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND) return 1; } @@ -4868,12 +4861,10 @@ num_sign_bit_copies1 (const_rtx x, machi break; case MEM: -#ifdef LOAD_EXTEND_OP /* Some RISC machines sign-extend all loads of smaller than a word. */ if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) return MAX (1, ((int) bitwidth - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1)); -#endif break; case CONST_INT: @@ -4910,7 +4901,6 @@ num_sign_bit_copies1 (const_rtx x, machi - bitwidth))); } -#ifdef LOAD_EXTEND_OP /* For paradoxical SUBREGs on machines where all register operations affect the entire register, just look inside. Note that we are passing MODE to the recursive call, so the number of sign bit copies @@ -4927,7 +4917,6 @@ num_sign_bit_copies1 (const_rtx x, machi && MEM_P (SUBREG_REG (x))) return cached_num_sign_bit_copies (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#endif break; case SIGN_EXTRACT: