From patchwork Thu Oct 31 16:02:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 178205 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3044991ill; Thu, 31 Oct 2019 09:03:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqzAlHKGx6gMtQq92lbApcQB2ycL/8wq1o3s1U3an5bXVtEMRCoVeB9zvvcRbR5BYjR6RiFK X-Received: by 2002:aa7:cd59:: with SMTP id v25mr7045263edw.26.1572537789018; Thu, 31 Oct 2019 09:03:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572537789; cv=none; d=google.com; s=arc-20160816; b=QzlooZqusormob7jsjoh7T1Ya0uiH/ca3RUrGfZzwfiHpKJFao9n2yiVAuyYw8KXCM 7Z0jI5no8Piu68fDbPqW2ZrsjrVlR8GM0iPNvpGl1hYtSCoYkEkfDhBr9CaAIJ9AJ6lc O3kIQPltLbv65U3hEWcQvKV9pSXuR2Ao6V5PfUaBvCo8LLmrLIZLrSKjnqUNDNuXcwu0 HZ2bKu96u53I03SKF15yQw7ntbhyYOq8z3n2X3A3DREjqFioyOZSGDB7fXqoSEnaxbAy U3jFf1aoMEfqehtayRjBrKP6VWb4J0SNZDPWY++ttkVHzOQ2OICVfCs78+VXFKz4B2rW EmRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:date:message-id:subject:from:to :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature; bh=bABLaK0y5355/uoCwVIWUY4KqS+uDawknaIj23I5gN4=; b=D7zPHkeYkR6cTrfPDA1Qgkmym7/9/kiD979eI9nDlhE6P0kGFKuC+9a+L4do780suH jZtf6/LVbPcUzNsBgPzoG57Yd7BdLaJ0bRkHG8jKi/Xz9eik2l8GCef7wHVBde8oCZzb ZDWDnLjxdemSJeGkgL/ynoKE7w9LXhf5sZajq4FqgYEwqQKf7s+1ukzAIh9W9e/YDUP5 J81aTrVRQeHdHAulxgIs0PSFqpIcMdaHEQhNbpfOWfIThH5RUNooWg/k4xttebPKhXml FHpV9AIMbMIL19ii3W31YRUrUQwTlvvHdolYtfukT+l2lhoEUic2uYS9JvZki7N4wi6K Nfkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=slxwT2jt; spf=pass (google.com: domain of gcc-patches-return-512163-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-512163-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id b47si4388594edc.129.2019.10.31.09.03.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Oct 2019 09:03:09 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-512163-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=slxwT2jt; spf=pass (google.com: domain of gcc-patches-return-512163-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-512163-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=KM72KGNB/rxHjuwtYA/7++CWKdnFt94/eeye0RoWd3Nznt5kLY FeR9tCZU8c6FJeG/o/PPKFvFAuu3g7jgoZx22Sz1hqwkgTv5lCDRoSsJvassbXqc DVfSOyf2b+e5/uW4a+C0ZHPf9bmi9q+DZ9o3OKptnDR473JOB/6XQnbHc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=CKxrD7HwxhdShYuxMFYOEwHuOUM=; b=slxwT2jtzw2AREOAmofh Ujd6cvVX6aY7bqIC3GGzU/elsN8VpnIkPTiSruMydHzM6gRXJ8KUfop2P2wiZAQt BeQRRFTqZX36tKFRKrlM4aZ6E0pq2EdQMF/eM1ygUgyoY+UtlL8romK1mga31HhS vSB3SrcoerWkCgiv46aTV/g= Received: (qmail 92247 invoked by alias); 31 Oct 2019 16:02:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 92238 invoked by uid 89); 31 Oct 2019 16:02:54 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=mr, shifted, SBC, !CONST_INT_P X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 31 Oct 2019 16:02:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D86B41F1; Thu, 31 Oct 2019 09:02:51 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.225]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5C22B3F71E; Thu, 31 Oct 2019 09:02:51 -0700 (PDT) To: "gcc-patches@gcc.gnu.org" From: "Richard Earnshaw (lists)" Subject: [arm] Pattern match insns for a + ~b + Carry Message-ID: <324ecbee-97f0-b98a-9978-98100fc988bf@arm.com> Date: Thu, 31 Oct 2019 16:02:49 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 On ARM, the SBC instruction is defined as Ra - Rb - ~C where C is the carry flag. But -Rb = ~Rb + 1, so this is equivalent to Ra + ~Rb + 1 - ~C which then simplifies to Ra + ~Rb + C which is essentially an add-with-carry with one operand inverted. We can define RTL patterns to match this. In thumb2 we can only match when the operands are both registers, but in Arm state we can also use RSC to match when Rn is either a constant or a shifted operand. This overall simplifies some cases of 64-bit arithmetic, for example, int64_t f (int64_t a, int64_t b) { return a + ~b; } will now compile to MVN R2, R2 ADDS R0, R0, R2 SBC R1, R1, R3 * config/arm/arm.md (add_not_cin): New insn. (add_not_shift_cin): Likewise. Committed. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ae77cc377f6..4f035cbfddd 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1662,6 +1662,41 @@ (define_insn "rsbsi_carryin_reg" (set_attr "type" "adc_imm")] ) +;; SBC performs Rn - Rm - ~C, but -Rm = ~Rm + 1 => Rn + ~Rm + 1 - ~C +;; => Rn + ~Rm + C, which is essentially ADC Rd, Rn, ~Rm +(define_insn "*add_not_cin" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (plus:SI + (plus:SI (not:SI (match_operand:SI 1 "s_register_operand" "r,r")) + (match_operand:SI 3 "arm_carry_operation" "")) + (match_operand:SI 2 "arm_rhs_operand" "r,I")))] + "TARGET_ARM || (TARGET_THUMB2 && !CONST_INT_P (operands[2]))" + "@ + sbc%?\\t%0, %2, %1 + rsc%?\\t%0, %1, %2" + [(set_attr "conds" "use") + (set_attr "predicable" "yes") + (set_attr "arch" "*,a") + (set_attr "type" "adc_reg,adc_imm")] +) + +;; On Arm we can also use the same trick when the non-inverted operand is +;; shifted, using RSC. +(define_insn "add_not_shift_cin" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (plus:SI + (plus:SI (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "shift_amount_operand" "M,r")]) + (not:SI (match_operand:SI 4 "s_register_operand" "r,r"))) + (match_operand:SI 5 "arm_carry_operation" "")))] + "TARGET_ARM" + "rsc%?\\t%0, %4, %1%S3" + [(set_attr "conds" "use") + (set_attr "predicable" "yes") + (set_attr "type" "alu_shift_imm,alu_shift_reg")] +) + (define_insn "cmpsi3_carryin_out" [(set (reg: CC_REGNUM) (compare: