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[209.132.180.131]) by mx.google.com with ESMTPS id gr3si18759799pbc.98.2014.11.12.08.58.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Nov 2014 08:58:22 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-383894-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 10101 invoked by alias); 12 Nov 2014 16:58:09 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10086 invoked by uid 89); 12 Nov 2014 16:58:08 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: foss-mx-na.foss.arm.com Received: from foss-mx-na.foss.arm.com (HELO foss-mx-na.foss.arm.com) (217.140.108.86) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Nov 2014 16:58:06 +0000 Received: from foss-smtp-na-1.foss.arm.com (unknown [10.80.61.8]) by foss-mx-na.foss.arm.com (Postfix) with ESMTP id 5A2D566 for ; Wed, 12 Nov 2014 10:57:51 -0600 (CST) Received: from collaborate-mta1.arm.com (highbank-bc01-b06.austin.arm.com [10.112.81.134]) by foss-smtp-na-1.foss.arm.com (Postfix) with ESMTP id 133C95FAD7 for ; Wed, 12 Nov 2014 10:57:48 -0600 (CST) Received: from [10.1.209.40] (e105545-lin.cambridge.arm.com [10.1.209.40]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 9C6CA13F78C for ; Wed, 12 Nov 2014 10:57:47 -0600 (CST) Message-ID: <54639197.2030505@arm.com> Date: Wed, 12 Nov 2014 16:57:59 +0000 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch ARM] Replace dmb sy with dmb ish X-IsSubscribed: yes X-Original-Sender: ramana.radhakrishnan@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::235 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hans Boehm pointed out that we were using dmb sy instead of dmb ish. Given that the ARM-ARM says that the inner shareability domain is really the one that contains all PE's controlled by a single hypervisor or operating system, it would be safe to replace all dmb sy's with dmb ish's. This is also in line with what we do in the AArch64 backend. Will apply after a test run tonight on armhf. regards Ramana * config/arm/sync.md (memory_barrier): Use dmb ish. commit fca60730dee3281db4b688d9029ef08688507843 Author: Ramana Radhakrishnan Date: Fri Sep 26 09:08:20 2014 +0100 Use dmb ish instead of dmb sy for ARM. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 06c4f0a..0614c50 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2014-09-26 Ramana Radhakrishnan + + * config/arm/sync.md (memory_barrier): Use dmb ish. + 2014-09-25 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index aa8e9ab..2f4f478 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -50,10 +50,9 @@ { if (TARGET_HAVE_DMB) { - /* Note we issue a system level barrier. We should consider issuing - a inner shareabilty zone barrier here instead, ie. "DMB ISH". */ - /* ??? Differentiate based on SEQ_CST vs less strict? */ - return "dmb\tsy"; + /* We used to issue a system level barrier. We now issue an + inner shareabilty zone barrier here instead, ie. "DMB ISH". */ + return "dmb\tish"; } if (TARGET_HAVE_DMB_MCR)