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[209.132.180.131]) by mx.google.com with ESMTPS id o1si2028875pde.256.2014.11.20.00.48.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Nov 2014 00:48:10 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-385247-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 12028 invoked by alias); 20 Nov 2014 08:47:58 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 12017 invoked by uid 89); 20 Nov 2014 08:47:58 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: foss-mx-na.foss.arm.com Received: from foss-mx-na.foss.arm.com (HELO foss-mx-na.foss.arm.com) (217.140.108.86) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 20 Nov 2014 08:47:56 +0000 Received: from foss-smtp-na-1.foss.arm.com (unknown [10.80.61.8]) by foss-mx-na.foss.arm.com (Postfix) with ESMTP id 44AE0DA; Thu, 20 Nov 2014 02:47:51 -0600 (CST) Received: from collaborate-mta1.arm.com (highbank-bc01-b06.austin.arm.com [10.112.81.134]) by foss-smtp-na-1.foss.arm.com (Postfix) with ESMTP id E29E15FAD7; Thu, 20 Nov 2014 02:47:48 -0600 (CST) Received: from [10.1.209.40] (e105545-lin.cambridge.arm.com [10.1.209.40]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 00E9E13F61D; Thu, 20 Nov 2014 02:47:47 -0600 (CST) Message-ID: <546DAAB3.1040307@arm.com> Date: Thu, 20 Nov 2014 08:47:47 +0000 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "Yangfei (Felix)" , "gcc-patches@gcc.gnu.org" CC: Chenshanyao , Kugan Subject: Re: [PATCH, PR63742][ARM] Fix arm *movhi_insn_arch4 pattern for big-endian References: <545A039D.104@arm.com> <546B053E.7090503@arm.com> <546B34A5.2030602@arm.com> <546B3FE8.30907@arm.com> In-Reply-To: X-IsSubscribed: yes X-Original-Sender: ramana.radhakrishnan@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22d as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 19/11/14 09:29, Yangfei (Felix) wrote: >>> Sorry for missing the point. It seems to me that 't2' here will conflict with >> condition of the pattern *movhi_insn_arch4: >>> "TARGET_ARM >>> && arm_arch4 >>> && (register_operand (operands[0], HImode) >>> || register_operand (operands[1], HImode))" >>> >>> #define TARGET_ARM (! TARGET_THUMB) >>> /* 32-bit Thumb-2 code. */ >>> #define TARGET_THUMB2 (TARGET_THUMB && >> arm_arch_thumb2) >>> >> >> Bah, Indeed ! - I misremembered the t2 there, my mistake. >> >> Yes you are right there, but what I'd like you to do is to use that mechanism >> rather than putting all this logic in the predicate. >> >> So, I'd prefer you to add a v6t2 to the values for the "arch" attribute, don't forget >> to update the comments above. >> >> and in arch_enabled you need to enforce this with >> >> (and (eq_attr "arch" "v6t2") >> (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2")) >> (const_string "yes") >> >> And in the pattern use v6t2 ... >> >> arm_arch_thumb2 implies that this is at the architecture level of v6t2. >> Therefore TARGET_ARM && arm_arch_thumb2 implies ARM state. > > > Hi Ramana, > Thank you for your suggestions. I rebased the patch on the latest trunk and updated it accordingly. > As this patch will not work for architectures older than armv6t2, I also prefer Thomas's patch to fix for them. > I am currently performing test for this patch. Assuming no issues pops up, OK for the trunk? > And is it necessary to backport this patch to the 4.8 & 4.9 branches? > I've applied the following as obvious after Kugan mentioned on IRC this morning noticing a movwne r0, #-32768. Obviously this won't be accepted as is by the assembler and we should be using the %L character. Applied to trunk as obvious. Felix, How did you test this patch ? regards Ramana 2014-11-20 Ramana Radhakrishnan PR target/59593 * config/arm/arm.md (*movhi_insn): Use right formatting for immediate. > > Index: gcc/ChangeLog > =================================================================== > --- gcc/ChangeLog (revision 217717) > +++ gcc/ChangeLog (working copy) > @@ -1,3 +1,11 @@ > +2014-11-19 Felix Yang > + Shanyao Chen > + > + PR target/59593 > + * config/arm/arm.md (define_attr "arch"): Add v6t2. > + (define_attr "arch_enabled"): Add test for the above. > + (*movhi_insn_arch4): Add new alternative. > + > 2014-11-18 Felix Yang > > * config/aarch64/aarch64.c (doloop_end): New pattern. > Index: gcc/config/arm/arm.md > =================================================================== > --- gcc/config/arm/arm.md (revision 217717) > +++ gcc/config/arm/arm.md (working copy) > @@ -125,9 +125,10 @@ > ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for > ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6" > ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without > -; arm_arch6. This attribute is used to compute attribute "enabled", > -; use type "any" to enable an alternative in all cases. > -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3" > +; arm_arch6. "v6t2" for Thumb-2 with arm_arch6. This attribute is > +; used to compute attribute "enabled", use type "any" to enable an > +; alternative in all cases. > +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3" > (const_string "any")) > > (define_attr "arch_enabled" "no,yes" > @@ -162,6 +163,10 @@ > (match_test "TARGET_32BIT && !arm_arch6")) > (const_string "yes") > > + (and (eq_attr "arch" "v6t2") > + (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2")) > + (const_string "yes") > + > (and (eq_attr "arch" "avoid_neon_for_64bits") > (match_test "TARGET_NEON") > (not (match_test "TARGET_PREFER_NEON_64BITS"))) > @@ -6288,8 +6293,8 @@ > > ;; Pattern to recognize insn generated default case above > (define_insn "*movhi_insn_arch4" > - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") > - (match_operand:HI 1 "general_operand" "rIk,K,r,mi"))] > + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r") > + (match_operand:HI 1 "general_operand" "rIk,K,n,r,mi"))] > "TARGET_ARM > && arm_arch4 > && (register_operand (operands[0], HImode) > @@ -6297,16 +6302,19 @@ > "@ > mov%?\\t%0, %1\\t%@ movhi > mvn%?\\t%0, #%B1\\t%@ movhi > + movw%?\\t%0, %1\\t%@ movhi > str%(h%)\\t%1, %0\\t%@ movhi > ldr%(h%)\\t%0, %1\\t%@ movhi" > [(set_attr "predicable" "yes") > - (set_attr "pool_range" "*,*,*,256") > - (set_attr "neg_pool_range" "*,*,*,244") > + (set_attr "pool_range" "*,*,*,*,256") > + (set_attr "neg_pool_range" "*,*,*,*,244") > + (set_attr "arch" "*,*,v6t2,*,*") > (set_attr_alternative "type" > [(if_then_else (match_operand 1 "const_int_operand" "") > (const_string "mov_imm" ) > (const_string "mov_reg")) > (const_string "mvn_imm") > + (const_string "mov_imm") > (const_string "store1") > (const_string "load1")])] > ) > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 3a6e0b0..a52716d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6302,7 +6302,7 @@ "@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi - movw%?\\t%0, %1\\t%@ movhi + movw%?\\t%0, %L1\\t%@ movhi str%(h%)\\t%1, %0\\t%@ movhi ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "predicable" "yes")