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[209.132.180.131]) by mx.google.com with ESMTPS id t5si11981256pbs.119.2015.09.18.02.05.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Sep 2015 02:05:15 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-407756-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 55045 invoked by alias); 18 Sep 2015 09:05:01 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 55028 invoked by uid 89); 18 Sep 2015 09:05:00 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Sep 2015 09:04:58 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-17-eTIP5HWUT5-5H6TSpde2xQ-1; Fri, 18 Sep 2015 10:04:53 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Sep 2015 10:04:52 +0100 Message-ID: <55FBD3B4.9050709@arm.com> Date: Fri, 18 Sep 2015 10:04:52 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Christian Bruel , "gcc-patches@gcc.gnu.org" , Ramana Radhakrishnan Subject: Re: [PATCH 4/4] [ARM] Add attribute/pragma target fpu= References: <55F6D9FF.4030600@st.com> <55F7F75E.4070800@st.com> In-Reply-To: <55F7F75E.4070800@st.com> X-MC-Unique: eTIP5HWUT5-5H6TSpde2xQ-1 X-IsSubscribed: yes X-Original-Sender: kyrylo.tkachov@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::234 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 15/09/15 11:47, Christian Bruel wrote: > > On 09/14/2015 04:30 PM, Christian Bruel wrote: >> Finally, the final part of the patch set does the attribute target >> parsing and checking, redefines the preprocessor macros and implements >> the inlining rules. >> >> testcases and documentation included. >> > new version to remove a shadowed remnant piece of code. > > > > thanks > > > > Christian > > + /* OK to inline between different modes. + Function with mode specific instructions, e.g using asm, + must be explicitely protected with noinline. */ s/explicitely/explicitly/ + const struct arm_fpu_desc *fpu_desc1 + = &all_fpus[caller_opts->x_arm_fpu_index]; + const struct arm_fpu_desc *fpu_desc2 + = &all_fpus[callee_opts->x_arm_fpu_index]; Please call these caller_fpu and callee_fpu, it's much easier to reason about the inlining rules that way + + /* Can't inline NEON extension if the caller doesn't support it. */ + if (ARM_FPU_FSET_HAS (fpu_desc2->features, FPU_FL_NEON) + && ! ARM_FPU_FSET_HAS (fpu_desc1->features, FPU_FL_NEON)) + return false; + + /* Can't inline CRYPTO extension if the caller doesn't support it. */ + if (ARM_FPU_FSET_HAS (fpu_desc2->features, FPU_FL_CRYPTO) + && ! ARM_FPU_FSET_HAS (fpu_desc1->features, FPU_FL_CRYPTO)) + return false; + We also need to take into account FPU_FL_FP16... In general what we want is for the callee FPU features to be a subset of the callers features, similar to the way we handle the x_aarch64_isa_flags handling in aarch64_can_inline_p from the aarch64 port. I think that's the way to go here rather than explicitly writing down a check for each feature. @@ -242,6 +239,8 @@ /* Update macros. */ gcc_assert (cur_opt->x_target_flags == target_flags); + /* This one can be redefined by the pragma without warning. */ + cpp_undef (parse_in, "__ARM_FP"); arm_cpu_builtins (parse_in); Could you elaborate why the cpp_undef here? If you want to undefine __ARM_FP so you can redefine it to a new value in arm_cpu_builtins then I think you should just undefine it in that function. diff -ruN gnu_trunk.p3/gcc/gcc/doc/invoke.texi gnu_trunk.p4/gcc/gcc/doc/invoke.texi --- gnu_trunk.p3/gcc/gcc/doc/invoke.texi 2015-09-10 12:21:00.698911244 +0200 +++ gnu_trunk.p4/gcc/gcc/doc/invoke.texi 2015-09-14 10:27:20.281932581 +0200 @@ -13360,6 +13363,8 @@ floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision. +You can also set the fpu name at function level by using the @code{target("mfpu=")} function attributes (@pxref{ARM Function Attributes}) or pragmas (@pxref{Function Specific Option Pragmas}). + s/"mfpu="/"fpu=" --- gnu_trunk.p3/gcc/gcc/testsuite/gcc.target/arm/attr-neon.c 1970-01-01 01:00:00.000000000 +0100 +++ gnu_trunk.p4/gcc/gcc/testsuite/gcc.target/arm/attr-neon.c 2015-09-14 16:12:08.449698268 +0200 @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3 -mfloat-abi=softfp -ftree-vectorize" } */ + +void +f3(int n, int x[], int y[]) { + int i; + for (i = 0; i < n; ++i) + y[i] = x[i] << 3; +} + What if GCC has been configured with --with-fpu=neon? Then f3 will be compiled assuming NEON. You should add a -mfpu=vfp to the dg-options.