From patchwork Thu Oct 1 13:00:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 54366 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f197.google.com (mail-lb0-f197.google.com [209.85.217.197]) by patches.linaro.org (Postfix) with ESMTPS id 2F4E0205D0 for ; Thu, 1 Oct 2015 13:01:09 +0000 (UTC) Received: by lbbti1 with SMTP id ti1sf5711981lbb.3 for ; Thu, 01 Oct 2015 06:01:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mailing-list:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:sender :delivered-to:message-id:date:from:user-agent:mime-version:to:cc :subject:content-type:x-original-sender :x-original-authentication-results; bh=NyfF3/o3Hu/Y+qQ/iNXtyhUkSnb7BX5l0O8iKW6jAKY=; b=ReqQApbT1k+lzL68AY3EvcMcRSw5HHz5RPl1zgzRjUVCFBJV5uUSpl6XDskiRzDtV/ Ow27kIgPw1ftG6eLhM7fcsSKOY4d1BBUyJC6Ka/rcNwWpe6MMp8ClerM1XT0gwE8Au14 TgCr62Op7qmXydVeWnUot3U+4asjQ3PT0Hkhw5MdxJofzXcZMF9eSFexGOXK3ZNKG0YJ W5Dppz15FbRPmT7vvE4H9fgM4u/4EAFdpMqrTdmHCCW1h+ap7A5tIvKzsmD+1LXbYCSn yeDowZz+C8GKFvVz3dx6/0210OzCuIqgQk16Ski/zLFaJdhF8wE5BcHdqGcJ8nsOYPmz h5pQ== X-Gm-Message-State: ALoCoQlbeNWniWZ9DZlG/lUQZcK97mP35gGs+C38LyRBHa3Sd2XbQ4I/LUcx9dxLkHSpT6IWM9yC X-Received: by 10.152.181.2 with SMTP id ds2mr562379lac.5.1443704467663; Thu, 01 Oct 2015 06:01:07 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.25.20.203 with SMTP id 72ls99820lfu.95.gmail; Thu, 01 Oct 2015 06:01:07 -0700 (PDT) X-Received: by 10.152.198.204 with SMTP id je12mr2916915lac.7.1443704467519; Thu, 01 Oct 2015 06:01:07 -0700 (PDT) Received: from mail-lb0-x22c.google.com (mail-lb0-x22c.google.com. [2a00:1450:4010:c04::22c]) by mx.google.com with ESMTPS id h2si2794409lag.122.2015.10.01.06.01.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Oct 2015 06:01:07 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22c as permitted sender) client-ip=2a00:1450:4010:c04::22c; Received: by lbwr8 with SMTP id r8so8691140lbw.2 for ; Thu, 01 Oct 2015 06:01:07 -0700 (PDT) X-Received: by 10.112.163.131 with SMTP id yi3mr2895624lbb.36.1443704467337; Thu, 01 Oct 2015 06:01:07 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp594965lbq; Thu, 1 Oct 2015 06:01:05 -0700 (PDT) X-Received: by 10.50.57.84 with SMTP id g20mr3206864igq.18.1443704464668; Thu, 01 Oct 2015 06:01:04 -0700 (PDT) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id d89si4702963ioj.5.2015.10.01.06.01.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Oct 2015 06:01:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-408834-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 58258 invoked by alias); 1 Oct 2015 13:00:50 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 58234 invoked by uid 89); 1 Oct 2015 13:00:49 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Oct 2015 13:00:47 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-16-RZ6rw58aTxqodt_48y7ljQ-1; Thu, 01 Oct 2015 14:00:41 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Oct 2015 14:00:41 +0100 Message-ID: <560D2E79.90700@arm.com> Date: Thu, 01 Oct 2015 14:00:41 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives X-MC-Unique: RZ6rw58aTxqodt_48y7ljQ-1 X-IsSubscribed: yes X-Original-Sender: kyrylo.tkachov@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22c as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi all, As part of the SWITCHABLE_TARGET work I inadvertently changed the behaviour of -mgeneral-regs-only with respect to the .arch directives that we emit. The behaviour of -mgeneral-regs-only in GCC 5 and earlier is such that it disallows the usage of FP/SIMD registers but does *not* stop the compiler from emitting the +fp,+simd etc extensions in the .arch directive of the generated assembly. This is to accommodate users who may want to write inline assembly in a file compiled with -mgeneral-regs-only. This patch restores the trunk behaviour in that respect to that of GCC 5 and the documentation for the option is tweaked a bit to reflect that. Bootstrapped and tested on aarch64. Ok for trunk? Thanks, Kyrill 2015-10-01 Kyrylo Tkachov * config/aarch64/aarch64.c (aarch64_override_options_internal): Do not alter target_flags due to TARGET_GENERAL_REGS_ONLY_P. * doc/invoke.texi (AArch64 options): Mention that -mgeneral-regs-only does not affect the assembler directives. 2015-10-01 Kyrylo Tkachov * gcc.target/aarch64/mgeneral-regs_4.c: New test. commit bd99347f0dad9346dc16ffc13cd423a4889ae339 Author: Kyrylo Tkachov Date: Fri Sep 11 09:40:44 2015 +0100 [AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 115c3a7..81e0eb0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7658,19 +7658,6 @@ aarch64_override_options_internal (struct gcc_options *opts) if (opts->x_flag_strict_volatile_bitfields < 0 && abi_version_at_least (2)) opts->x_flag_strict_volatile_bitfields = 1; - /* -mgeneral-regs-only sets a mask in target_flags, make sure that - aarch64_isa_flags does not contain the FP/SIMD/Crypto feature flags - in case some code tries reading aarch64_isa_flags directly to check if - FP is available. Reuse the aarch64_parse_extension machinery since it - knows how to disable any other flags that fp implies. */ - if (TARGET_GENERAL_REGS_ONLY_P (opts->x_target_flags)) - { - /* aarch64_parse_extension takes char* rather than const char* because - it is usually called from within other parsing functions. */ - char tmp_str[] = "+nofp"; - aarch64_parse_extension (tmp_str, &opts->x_aarch64_isa_flags); - } - initialize_aarch64_code_model (opts); initialize_aarch64_tls_size (opts); diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 547ee2d..e8067f2 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12304,10 +12304,9 @@ Generate big-endian code. This is the default when GCC is configured for an @item -mgeneral-regs-only @opindex mgeneral-regs-only -Generate code which uses only the general-purpose registers. This is equivalent -to feature modifier @option{nofp} of @option{-march} or @option{-mcpu}, except -that @option{-mgeneral-regs-only} takes precedence over any conflicting feature -modifier regardless of sequence. +Generate code which uses only the general-purpose registers. This will prevent +the compiler from using floating-point and Advanced SIMD registers but will not +impose any restrictions on the assembler. @item -mlittle-endian @opindex mlittle-endian diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c new file mode 100644 index 0000000..8eb50aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c @@ -0,0 +1,9 @@ +/* { dg-options "-mgeneral-regs-only -march=armv8-a+simd+fp -O2" } */ + +int +test (void) +{ + return 1; +} + +/* { dg-final { scan-assembler "\.arch.*fp.*simd" } } */