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[209.132.180.131]) by mx.google.com with ESMTPS id z31si28132943plb.1.2016.12.08.01.35.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Dec 2016 01:35:38 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-443769-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-443769-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-443769-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=XUgyFYSN8VXHKqVWSUNn9FCWaD3q2z1v5oSyeoh6nPq MGy6SHKndmNq08jbAnT5FNgYqG9pcYUscNBTz2sLWsLxasf3DIXI1PctBZAg2E2u XpwENW/M5D9H9wjxCMX1K7D5Nx6AmWzJijOGbP1lNSKFS4UGeY9fWPmMWjrwb39c = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=Idp554FCg5ze9iwjs8kCF4Nm4jA=; b=f76R/qGgQAJVemKhJ hPGcB0rx02w4IXufnC25v0aAB4FuDQTYobATTrbL2U5ECjtt0wxaAGEY8hNJnQp6 sE4KGgBI5ngYGWdPzBNLpXDMm6dwHapI5twyh3ceF/hbXvKKG757LYu18utGbJCA XO+MvSEHZQ2dzRQIvKb7/vi0Qs= Received: (qmail 94997 invoked by alias); 8 Dec 2016 09:35:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 94965 invoked by uid 89); 8 Dec 2016 09:35:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=gpi, (unknown), xxx, risk X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Dec 2016 09:35:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC940CF6; Thu, 8 Dec 2016 01:35:11 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E091F3F51A; Thu, 8 Dec 2016 01:35:10 -0800 (PST) Message-ID: <5849294D.6040003@foss.arm.com> Date: Thu, 08 Dec 2016 09:35:09 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] Split X-reg UBFIZ into W-reg LSL when possible Hi all, Similar to the previous patch this transforms X-reg UBFIZ instructions into W-reg LSL instructions when the UBFIZ operands add up to 32, so we can take advantage of the implicit zero-extension to DImode when writing to a W-register. This is done by splitting the existing *andim_ashift_bfi pattern into its two SImode and DImode specialisations and changing the DImode pattern into a define_insn_and_split that splits into a zero-extended SImode ashift when the operands match up. So for the code in the testcase we generate: LSL W0, W0, 5 instead of: UBFIZ X0, X0, 5, 27 Bootstrapped and tested on aarch64-none-linux-gnu. Since we're in stage 3 perhaps this is not for GCC 6, but it is fairly low risk. I'm happy for it to wait for the next release if necessary. Thanks, Kyrill 2016-12-08 Kyrylo Tkachov * config/aarch64/aarch64.md (*andim_ashift_bfiz): Split into... (*andim_ashiftsi_bfiz): ...This... (*andim_ashiftdi_bfiz): ...And this. Add split to ashift when possible. 2016-12-08 Kyrylo Tkachov * gcc.target/aarch64/ubfiz_lsl_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index a6f659c26bb5156d652b6c1f09123e682e9ff648..d1083381876572616a61f8f59d523f258dd077f4 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4459,13 +4459,33 @@ (define_insn "*_shft_" ;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below -(define_insn "*andim_ashift_bfiz" - [(set (match_operand:GPI 0 "register_operand" "=r") - (and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r") +(define_insn "*andim_ashiftsi_bfiz" + [(set (match_operand:SI 0 "register_operand" "=r") + (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n")) + (match_operand 3 "const_int_operand" "n")))] + "aarch64_mask_and_shift_for_ubfiz_p (SImode, operands[3], operands[2])" + "ubfiz\\t%w0, %w1, %2, %P3" + [(set_attr "type" "bfx")] +) + +(define_insn_and_split "*andim_ashiftdi_bfiz" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand 2 "const_int_operand" "n")) (match_operand 3 "const_int_operand" "n")))] - "aarch64_mask_and_shift_for_ubfiz_p (mode, operands[3], operands[2])" - "ubfiz\\t%0, %1, %2, %P3" + "aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2])" + "ubfiz\\t%x0, %x1, %2, %P3" + ;; When the bitposition and width of the equivalent extraction add up to 32 + ;; we can use a W-reg LSL instruction taking advantage of the implicit + ;; zero-extension of the X-reg. + "&& (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3]))) + == GET_MODE_BITSIZE (SImode)" + [(set (match_dup 0) + (zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))] + { + operands[4] = gen_lowpart (SImode, operands[1]); + } [(set_attr "type" "bfx")] ) diff --git a/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c new file mode 100644 index 0000000000000000000000000000000000000000..d3fd3f234f2324d71813298210fdcf0660ac45b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL. */ + +long long +f2 (long long x) +{ + return (x << 5) & 0xffffffff; +} + +/* { dg-final { scan-assembler "lsl\tw" } } */ +/* { dg-final { scan-assembler-not "ubfiz\tx" } } */