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[188.29.164.51]) by smtp.gmail.com with ESMTPSA id x19sm7000415wrd.10.2017.10.27.06.28.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Oct 2017 06:28:31 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@linaro.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [07/nn] [AArch64] Pass number of units to aarch64_reverse_mask References: <873764d8y3.fsf@linaro.org> Date: Fri, 27 Oct 2017 14:28:27 +0100 In-Reply-To: <873764d8y3.fsf@linaro.org> (Richard Sandiford's message of "Fri, 27 Oct 2017 14:19:48 +0100") Message-ID: <8760b0btz8.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 This patch passes the number of units to aarch64_reverse_mask, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-10-26 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64-protos.h (aarch64_reverse_mask): Take the number of units too. * config/aarch64/aarch64.c (aarch64_reverse_mask): Likewise. * config/aarch64/aarch64-simd.md (vec_load_lanesoi) (vec_store_lanesoi, vec_load_lanesci) (vec_store_lanesci, vec_load_lanesxi) (vec_store_lanesxi): Update accordingly. Reviewed-by: James Greenhalgh Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:00.601693018 +0100 +++ gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:04.192082112 +0100 @@ -365,7 +365,7 @@ bool aarch64_mask_and_shift_for_ubfiz_p bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx); bool aarch64_move_imm (HOST_WIDE_INT, machine_mode); bool aarch64_mov_operand_p (rtx, machine_mode); -rtx aarch64_reverse_mask (machine_mode); +rtx aarch64_reverse_mask (machine_mode, unsigned int); bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT); char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode); char *aarch64_output_simd_mov_immediate (rtx, unsigned, Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-10-27 14:12:00.603550436 +0100 +++ gcc/config/aarch64/aarch64.c 2017-10-27 14:12:04.193939530 +0100 @@ -13945,16 +13945,18 @@ aarch64_vectorize_vec_perm_const_ok (mac return ret; } +/* Generate a byte permute mask for a register of mode MODE, + which has NUNITS units. */ + rtx -aarch64_reverse_mask (machine_mode mode) +aarch64_reverse_mask (machine_mode mode, unsigned int nunits) { /* We have to reverse each vector because we dont have a permuted load that can reverse-load according to ABI rules. */ rtx mask; rtvec v = rtvec_alloc (16); - int i, j; - int nunits = GET_MODE_NUNITS (mode); - int usize = GET_MODE_UNIT_SIZE (mode); + unsigned int i, j; + unsigned int usize = GET_MODE_UNIT_SIZE (mode); gcc_assert (BYTES_BIG_ENDIAN); gcc_assert (AARCH64_VALID_SIMD_QREG_MODE (mode)); Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:00.602621727 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:04.193010821 +0100 @@ -4632,7 +4632,7 @@ (define_expand "vec_load_lanesoi" if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (OImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_simd_ld2 (tmp, operands[1])); emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask)); } @@ -4676,7 +4676,7 @@ (define_expand "vec_store_lanesoi" if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (OImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask)); emit_insn (gen_aarch64_simd_st2 (operands[0], tmp)); } @@ -4730,7 +4730,7 @@ (define_expand "vec_load_lanesci" if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (CImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_simd_ld3 (tmp, operands[1])); emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask)); } @@ -4774,7 +4774,7 @@ (define_expand "vec_store_lanesci" if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (CImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask)); emit_insn (gen_aarch64_simd_st3 (operands[0], tmp)); } @@ -4828,7 +4828,7 @@ (define_expand "vec_load_lanesxi" if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (XImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_simd_ld4 (tmp, operands[1])); emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask)); } @@ -4872,7 +4872,7 @@ (define_expand "vec_store_lanesxi" if (BYTES_BIG_ENDIAN) { rtx tmp = gen_reg_rtx (XImode); - rtx mask = aarch64_reverse_mask (mode); + rtx mask = aarch64_reverse_mask (mode, ); emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask)); emit_insn (gen_aarch64_simd_st4 (operands[0], tmp)); }