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[209.132.180.131]) by mx.google.com with ESMTPS id i1si9432124pld.970.2017.08.22.02.24.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Aug 2017 02:24:12 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-460692-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=WezTjzi4; spf=pass (google.com: domain of gcc-patches-return-460692-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-460692-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=O9xMGNcrx0JK8O1U7pzJ6as0IswhxuXMVnBMU23Vbw/JoObkqYsar Iyk52KYYjso8h+f54ADfeGAGRm7oSvvzvDhwDyhLnpC+AIk9Fnwl/51NgrtQ8Zh4 a3vwrAeEpr66/YPugC19SEUNGu/v8ujli57miLE0n5jBq4GvWwfcgs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=kSsP9u0PN1pHiT9iVGUFA1a/Gb0=; b=WezTjzi4HudtefSTGif3 uDNioYPgx/Tev+uKOutpiYypnbnjcI2pvDNSz9QuVs5OsrM3a0sCsb7Zu59nnmJf 9Dvlaheywkjog/B9YEAHN2v5Gz3dIFY5RZcoWegiFoc3YyyeA9OH6tjRJGqUiwvK 4SBRPXR1/7/wkXGUVrTawNQ= Received: (qmail 118524 invoked by alias); 22 Aug 2017 09:23:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 118500 invoked by uid 89); 22 Aug 2017 09:23:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=LDP X-HELO: mail-wr0-f177.google.com Received: from mail-wr0-f177.google.com (HELO mail-wr0-f177.google.com) (209.85.128.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 22 Aug 2017 09:23:51 +0000 Received: by mail-wr0-f177.google.com with SMTP id z91so118016858wrc.4 for ; Tue, 22 Aug 2017 02:23:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:date:message-id :user-agent:mime-version; bh=rPmrRlPmpWFwRzOfyo8JqWMcia8KFJuDQn1Lk5PtjDs=; b=NVQlGJnTzLDDmEcL3QmbkvIc/g8NkFETp5GUC6N11kyP9MdxDChPh0hy5qCdjvDJcl +2BIOiUJKwTeHvDTlnGkIh4CrmAf+KXrb62FVUHt3YPMDljZX3TvXcfXPYifDCV5wTeD PHaYxF4vsDUw1GTXFLAzXL2orroSahdhL4b7CyBSqh355QTiYhBJQuCKSPPVitZtPNOQ a4ymEL4+OYPJn3mEZjZUTSKt18rqRBXYwJCfUlIcu/KXRCgDxm4yB/yFKypSu1HfCM46 GTVanuebgMqtMSwYQh8zHQOcUxOwlcl2kkfTVoX8rVYPjOAeHXHhcz6LVg8PlGOJo593 4/vg== X-Gm-Message-State: AHYfb5iQ09yyMTx4Oq8uiZ1zfj6oS2xLtcyqjRdctpssesZ0AmOiell1 N7OeBS+P2aeesKAIvK+hLA== X-Received: by 10.223.148.103 with SMTP id 94mr23194wrq.174.1503393828833; Tue, 22 Aug 2017 02:23:48 -0700 (PDT) Received: from localhost ([95.145.139.63]) by smtp.gmail.com with ESMTPSA id q45sm10693482wrb.3.2017.08.22.02.23.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 02:23:48 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [AArch64] Tweak aarch64_classify_address interface Date: Tue, 22 Aug 2017 10:23:47 +0100 Message-ID: <8760dgc5wc.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Previously aarch64_classify_address used an rtx code to distinguish LDP/STP addresses from normal addresses; the code was PARALLEL to select LDP/STP and anything else to select normal addresses. This patch replaces that parameter with a dedicated enum. The SVE port will add another enum value that didn't map naturally to an rtx code. Tested on aarch64-linux-gnu. OK to install? 2017-08-22 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64-protos.h (aarch64_addr_query_type): New enum. (aarch64_legitimate_address_p): Use it instead of an rtx code. * config/aarch64/aarch64.c (aarch64_classify_address): Likewise. (aarch64_legitimate_address_p): Likewise. (aarch64_address_valid_for_prefetch_p): Update calls accordingly. (aarch64_legitimate_address_hook_p): Likewise. (aarch64_print_operand_address): Likewise. (aarch64_address_cost): Likewise. * config/aarch64/aarch64-simd.md (mov): Likewise. * config/aarch64/constraints.md (Uad): Likewise. * config/aarch64/predicates.md (aarch64_mem_pair_operand): Likewise. Reviewed-By: James Greenhalgh Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2017-08-03 10:40:55.900281836 +0100 +++ gcc/config/aarch64/aarch64-protos.h 2017-08-22 10:12:29.278432707 +0100 @@ -111,6 +111,19 @@ enum aarch64_symbol_type SYMBOL_FORCE_TO_MEM }; +/* Classifies the type of an address query. + + ADDR_QUERY_M + Query what is valid for an "m" constraint and a memory_operand + (the rules are the same for both). + + ADDR_QUERY_LDP_STP + Query what is valid for a load/store pair. */ +enum aarch64_addr_query_type { + ADDR_QUERY_M, + ADDR_QUERY_LDP_STP +}; + /* A set of tuning parameters contains references to size and time cost models and vectors for address cost calculations, register move costs and memory move costs. */ @@ -433,7 +446,8 @@ bool aarch64_float_const_representable_p #if defined (RTX_CODE) -bool aarch64_legitimate_address_p (machine_mode, rtx, RTX_CODE, bool); +bool aarch64_legitimate_address_p (machine_mode, rtx, + aarch64_addr_query_type, bool); machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); rtx aarch64_load_tp (rtx); Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-08-10 14:36:08.826443491 +0100 +++ gcc/config/aarch64/aarch64.c 2017-08-22 10:12:29.280432708 +0100 @@ -4385,21 +4385,21 @@ virt_or_elim_regno_p (unsigned regno) || regno == ARG_POINTER_REGNUM); } -/* Return true if X is a valid address for machine mode MODE. If it is, - fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in - effect. OUTER_CODE is PARALLEL for a load/store pair. */ +/* Return true if X is a valid address of type TYPE for machine mode MODE. + If it is, fill in INFO appropriately. STRICT_P is true if + REG_OK_STRICT is in effect. */ static bool aarch64_classify_address (struct aarch64_address_info *info, rtx x, machine_mode mode, - RTX_CODE outer_code, bool strict_p) + aarch64_addr_query_type type, bool strict_p) { enum rtx_code code = GET_CODE (x); rtx op0, op1; /* On BE, we use load/store pair for all large int mode load/stores. TI/TFmode may also use a load/store pair. */ - bool load_store_pair_p = (outer_code == PARALLEL + bool load_store_pair_p = (type == ADDR_QUERY_LDP_STP || mode == TImode || mode == TFmode || (BYTES_BIG_ENDIAN @@ -4631,7 +4631,8 @@ aarch64_address_valid_for_prefetch_p (rt struct aarch64_address_info addr; /* PRFM accepts the same addresses as DImode... */ - bool res = aarch64_classify_address (&addr, x, DImode, MEM, strict_p); + bool res = aarch64_classify_address (&addr, x, DImode, ADDR_QUERY_M, + strict_p); if (!res) return false; @@ -4667,19 +4668,18 @@ aarch64_legitimate_address_hook_p (machi { struct aarch64_address_info addr; - return aarch64_classify_address (&addr, x, mode, MEM, strict_p); + return aarch64_classify_address (&addr, x, mode, ADDR_QUERY_M, strict_p); } -/* Return TRUE if X is a legitimate address for accessing memory in - mode MODE. OUTER_CODE will be PARALLEL if this is a load/store - pair operation. */ +/* Return TRUE if X is a legitimate address of type TYPE for accessing + memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */ bool aarch64_legitimate_address_p (machine_mode mode, rtx x, - RTX_CODE outer_code, bool strict_p) + aarch64_addr_query_type type, bool strict_p) { struct aarch64_address_info addr; - return aarch64_classify_address (&addr, x, mode, outer_code, strict_p); + return aarch64_classify_address (&addr, x, mode, type, strict_p); } /* Split an out-of-range address displacement into a base and offset. @@ -5550,7 +5550,7 @@ aarch64_print_operand_address (FILE *f, { struct aarch64_address_info addr; - if (aarch64_classify_address (&addr, x, mode, MEM, true)) + if (aarch64_classify_address (&addr, x, mode, ADDR_QUERY_M, true)) switch (addr.type) { case ADDRESS_REG_IMM: @@ -6474,7 +6474,7 @@ aarch64_address_cost (rtx x, int cost = 0; info.shift = 0; - if (!aarch64_classify_address (&info, x, mode, c, false)) + if (!aarch64_classify_address (&info, x, mode, ADDR_QUERY_M, false)) { if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF) { Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-08-22 10:11:45.066232915 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2017-08-22 10:12:29.279432707 +0100 @@ -26,7 +26,7 @@ (define_expand "mov" if (GET_CODE (operands[0]) == MEM && !(aarch64_simd_imm_zero (operands[1], mode) && aarch64_legitimate_address_p (mode, operands[0], - PARALLEL, 1))) + ADDR_QUERY_LDP_STP, 1))) operands[1] = force_reg (mode, operands[1]); " ) Index: gcc/config/aarch64/constraints.md =================================================================== --- gcc/config/aarch64/constraints.md 2017-08-03 10:40:55.900281836 +0100 +++ gcc/config/aarch64/constraints.md 2017-08-22 10:12:29.280432708 +0100 @@ -161,7 +161,7 @@ (define_memory_constraint "Ump" A memory address suitable for a load/store pair operation." (and (match_code "mem") (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), - PARALLEL, 1)"))) + ADDR_QUERY_LDP_STP, 1)"))) (define_memory_constraint "Utv" "@internal Index: gcc/config/aarch64/predicates.md =================================================================== --- gcc/config/aarch64/predicates.md 2017-08-16 08:50:34.059622539 +0100 +++ gcc/config/aarch64/predicates.md 2017-08-22 10:12:29.281432708 +0100 @@ -174,8 +174,8 @@ (define_predicate "aarch64_mem_pair_offs (define_predicate "aarch64_mem_pair_operand" (and (match_code "mem") - (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL, - 0)"))) + (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), + ADDR_QUERY_LDP_STP, 0)"))) (define_predicate "aarch64_prefetch_operand" (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))