From patchwork Mon Nov 13 08:21:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 118717 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1523856qgn; Mon, 13 Nov 2017 00:22:09 -0800 (PST) X-Google-Smtp-Source: AGs4zMZcEC8H+YilNQT4AEdqegg5W00S00GBxnK594RHvo8/ZfhjYj4UXKZ4aWnzDSkV8UuuzGD3 X-Received: by 10.84.195.36 with SMTP id i33mr8504394pld.38.1510561329705; Mon, 13 Nov 2017 00:22:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510561329; cv=none; d=google.com; s=arc-20160816; b=HJ+wsVCTBvMRrUTBvZVjEVvS4Ig1Ao4Y8Xo6LumL1cYE6G6IOdW0pMDoOzNwm5Oz8x xKUYyMDKWfB/qrROnmquFxLWbFB6eqBcukA8lEYV8r3KOmBgZvDGItKQUKM5FObpAD6k KiuAfKtb8/xwMI8B0ZGdFV8hDugVzhkW8S/EwfSYYuQU2+nKG1/wmCphJcWkJHWybi28 W0AdrWl93AMCunxamqQNpGXLStTHvckMlOkFSr+aP1dphVBUj8GsYOKvqVSf7st/G7bz HXWNT7j9sHYk7VnLf8MiXJOmdJYRMZK4cAru835TG0Zj3u0W62+erfjAsE8lPg6BUKcY hugQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:date:subject:mail-followup-to:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=DbNWQb/ZaCVzvesRwN2Yd4tBEkkR5DYXv5gr64m8qtc=; b=tn5H26+7Ilfx2BJyurvPonYoWMczi7rOofD+dCcx/7EhTGCEFhzvH4LjI419rQHLJV WABIiygbKfTfV+FWlrb0FkSiKTZFc7qr2Fc8kmv9bDWQ1F3EgJjMj43Nc19T4HshO9sf LtphOb1ZUMo/lkYdNNoTdMU5UcqIkPGYQd2TY2iF0Ywem9a+P7gbNkaaP+trMQLe7Ti+ J2s8U6UB3lVFe8Ygw2UMoj+pkoZxlU3a4IbiAdA2NxSB1NJoL02zSJsHPMCh5Cklmsbw ZwzpBKkAoLdD50+3tOSscupuTNmfgH5T/yXFXWXKK5QIynDL+7iTEyF7eNA/xUB5Xye/ 2Hpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=VVO4nGbu; spf=pass (google.com: domain of gcc-patches-return-466617-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-466617-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id f30si14216228plf.32.2017.11.13.00.22.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Nov 2017 00:22:09 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-466617-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=VVO4nGbu; spf=pass (google.com: domain of gcc-patches-return-466617-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-466617-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=IHBTq1OpQie5DcP3/86xR6s6KW8EoxnO4ZA9jO3GIYyZWVgzu7jTD cQV6outl9/9eAxHe4MePjYl2jTxul7/TMUVS59zEBtgs7zYd5ojA5yPcTZwMkcAH 29kUCAUv9rRXzRB+QGzHPKrNrPNeA/cGUmMM7hjs95cLEF0GYFl6YI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=/zvEB5FdUxfEL5n8pj+PqCsEWIk=; b=VVO4nGbuzsLY+txYI+J4 LXnG6MLXIIaNaDLaRhfOEy79k10jjK6w2CnptZ43oBL1vN93TY32YKSpME5wwOVF RzzqJiCfpnuCUYFjj9IBLDEnE8sq/hEEgjjSkfmeMZ1jEG3tBYUEb/dNGSa+i3tu bGADj3WV9X2DDuzlo4pOW50= Received: (qmail 103527 invoked by alias); 13 Nov 2017 08:21:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 103510 invoked by uid 89); 13 Nov 2017 08:21:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Envelope-From:sk:richard, sk:immedia, 7329, 4508 X-HELO: mail-wm0-f51.google.com Received: from mail-wm0-f51.google.com (HELO mail-wm0-f51.google.com) (74.125.82.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 13 Nov 2017 08:21:51 +0000 Received: by mail-wm0-f51.google.com with SMTP id t139so13299568wmt.1 for ; Mon, 13 Nov 2017 00:21:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:date:message-id :user-agent:mime-version; bh=DbNWQb/ZaCVzvesRwN2Yd4tBEkkR5DYXv5gr64m8qtc=; b=WQsXqPhxSoJqw277S3xYSbkXC1XwQxvPouUFIhOhwl0AT9tOAE5UREhUlV5WNkXkgY R92K9fiZyrD/t0QDdvSCHgf9rWilSaxiEIuweK8bbkuK0Ji6vMPQCZ1XUavH3MOmbE0m LR66AXT8LeDhKKnQcD+nhEDhX+6kp/Cxipa4fAwHwDMb2Bui110tfUdKcOzkBNxtcXgH taArJBw53YQOvjDRbfoeQdbbedP5LUnCPU7Jo5PVjw0b8RQlIfouTsehesavPek2UCwC gvqRteax6dcK6gXX6+JzuJE4C4GhLEJjbYzVcc+wxOkzdvcsMbbPVGV0Io8gIoRVVMrP jYaA== X-Gm-Message-State: AJaThX4AsPFhpZ76rdvzj3WkfQILtU1M5DXVVR9PfcCNLi95qgFepLaz flajWymgFtUQLJDjZPKtDHXFEaSruG4= X-Received: by 10.28.7.82 with SMTP id 79mr5419480wmh.4.1510561309074; Mon, 13 Nov 2017 00:21:49 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id y15sm17844424wrc.96.2017.11.13.00.21.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 13 Nov 2017 00:21:48 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [committed] [AArch64] More aarch64_endian_lane_rtx Date: Mon, 13 Nov 2017 08:21:49 +0000 Message-ID: <87o9o6eggy.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 r254466 failed to update some uses of ENDIAN_LANE_N that were added after the patch was initially written, which meant that we were treating the mode number as an element count. Tested on aarch64-linux-gnu and aarch64_be-elf and installed as obvious. Sorry for the breakage... Richard 2017-11-13 Richard Sandiford gcc/ * config/aarch64/aarch64-simd.md (aarch64_store_lane0): Upddate call to ENDIAN_LANE_N. (aarch64_dot_lane): Use aarch64_endian_lane_rtx. (aarch64_dot_laneq): Likewise. (*aarch64_simd_vec_copy_lane): Update calls to ENDIAN_LANE_N and use aarch64_endian_lane_rtx. (*aarch64_simd_vec_copy_lane_): Likewise. Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-11-09 14:21:44.843800048 +0000 +++ gcc/config/aarch64/aarch64-simd.md 2017-11-13 08:18:32.555560682 +0000 @@ -173,7 +173,7 @@ (define_insn "aarch64_store_lane0" (vec_select: (match_operand:VALL_F16 1 "register_operand" "w") (parallel [(match_operand 2 "const_int_operand" "n")])))] "TARGET_SIMD - && ENDIAN_LANE_N (mode, INTVAL (operands[2])) == 0" + && ENDIAN_LANE_N (, INTVAL (operands[2])) == 0" "str\\t%1, %0" [(set_attr "type" "neon_store1_1reg")] ) @@ -450,8 +450,7 @@ (define_insn "aarch64_dot_lanedot\\t%0., %2., %3.4b[%4]"; } [(set_attr "type" "neon_dot")] @@ -466,8 +465,7 @@ (define_insn "aarch64_dot_laneqdot\\t%0., %2., %3.4b[%4]"; } [(set_attr "type" "neon_dot")] @@ -734,9 +732,9 @@ (define_insn "*aarch64_simd_vec_copy_lan (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { - int elt = ENDIAN_LANE_N (mode, exact_log2 (INTVAL (operands[2]))); + int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + operands[4] = aarch64_endian_lane_rtx (mode, INTVAL (operands[4])); return "ins\t%0.[%p2], %3.[%4]"; } @@ -755,10 +753,10 @@ (define_insn "*aarch64_simd_vec_copy_lan (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { - int elt = ENDIAN_LANE_N (mode, exact_log2 (INTVAL (operands[2]))); + int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, - INTVAL (operands[4]))); + operands[4] = aarch64_endian_lane_rtx (mode, + INTVAL (operands[4])); return "ins\t%0.[%p2], %3.[%4]"; }