From patchwork Fri Jun 19 16:43:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 50117 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f197.google.com (mail-wi0-f197.google.com [209.85.212.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B5FFA22903 for ; Fri, 19 Jun 2015 16:43:21 +0000 (UTC) Received: by wibdt2 with SMTP id dt2sf6648922wib.3 for ; Fri, 19 Jun 2015 09:43:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mailing-list:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:sender :delivered-to:mime-version:date:message-id:subject:from:to :content-type:x-original-sender:x-original-authentication-results; bh=/Gmc49HgK6hA6lOX16yOdOnzKSV/Gf9JcNVf76CXhfA=; b=EfyX7JZIZBp4e+QBQTzF2gqKxBpZ2dkAdRfd1PAM0Cy4kWgluW8mhMg1juKusaKMK7 WGLXXM5SqLGikP9q7NVt9xoVvWyPC8H1i3GKXS+5p9bmKUWUfjexMU1gGO7HQXfC0kaA /AlCSPiV+Eh6tMnH2Qe94oBmyy6+fjyR1Tzthwh7x2d+i0PorgCDGicy3PD2LretZZRr X53DBBNczo1cqErj7Izjq3SELHFi3nG+GwszW6X1EU9OcD/DRb4nD1sFWTtVqpJUuF5T 3iF4rZO5U19N8I6yGJFhtM8k19SAF9RoPGivY2BiPuYMVYuH7QqhHF8npZBGsspeyl7Y rb6g== X-Gm-Message-State: ALoCoQng7aYrxhKjEAEEs9N/fvE04zVbnYdlnuImmBE+4vqooq2DcyfAuB5KOztN5chHH/vQ+pR2 X-Received: by 10.180.90.106 with SMTP id bv10mr3948908wib.6.1434732201047; Fri, 19 Jun 2015 09:43:21 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.23.103 with SMTP id l7ls653979laf.35.gmail; Fri, 19 Jun 2015 09:43:20 -0700 (PDT) X-Received: by 10.152.5.65 with SMTP id q1mr18680669laq.110.1434732200889; Fri, 19 Jun 2015 09:43:20 -0700 (PDT) Received: from mail-la0-x22a.google.com (mail-la0-x22a.google.com. [2a00:1450:4010:c03::22a]) by mx.google.com with ESMTPS id dh9si6840995lac.35.2015.06.19.09.43.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jun 2015 09:43:20 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22a as permitted sender) client-ip=2a00:1450:4010:c03::22a; Received: by laka10 with SMTP id a10so77654763lak.0 for ; Fri, 19 Jun 2015 09:43:20 -0700 (PDT) X-Received: by 10.152.87.33 with SMTP id u1mr18935561laz.35.1434732200713; Fri, 19 Jun 2015 09:43:20 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp715155lbb; Fri, 19 Jun 2015 09:43:19 -0700 (PDT) X-Received: by 10.70.33.67 with SMTP id p3mr33510127pdi.126.1434732198682; Fri, 19 Jun 2015 09:43:18 -0700 (PDT) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id vk3si17137495pbc.139.2015.06.19.09.43.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jun 2015 09:43:18 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-400818-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 71551 invoked by alias); 19 Jun 2015 16:43:05 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 71515 invoked by uid 89); 19 Jun 2015 16:43:04 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-qk0-f171.google.com Received: from mail-qk0-f171.google.com (HELO mail-qk0-f171.google.com) (209.85.220.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 19 Jun 2015 16:43:03 +0000 Received: by qkeo142 with SMTP id o142so46578115qke.1 for ; Fri, 19 Jun 2015 09:43:01 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.140.133.18 with SMTP id 18mr23749515qhf.84.1434732181121; Fri, 19 Jun 2015 09:43:01 -0700 (PDT) Received: by 10.140.101.67 with HTTP; Fri, 19 Jun 2015 09:43:01 -0700 (PDT) Date: Fri, 19 Jun 2015 09:43:01 -0700 Message-ID: Subject: [PATCH, AARCH64] improve float/double 0.0 support From: Jim Wilson To: "gcc-patches@gcc.gnu.org" X-Original-Sender: jim.wilson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22a as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 This is a follow on to the long double 0.0 patch. The float and double support has similar problems and need similar fixes, though a little smaller in scope. Before the patch this testcase void sub1 (float *f) { *f = 0.0; } void sub2 (double *d) { *d = 0.0; } gives assembly code sub1: fmov s0, wzr str s0, [x0] ... sub2: fmov d0, xzr str d0, [x0] after the patch, the assembly code is sub1: str wzr, [x0] ... sub2: str xzr, [x0] The fixes are along the same lines as the earlier long double patch. The expander is changed so that a zero source isn't forced into a reg, the patterns are changed to allow a zero source, and the instruction types are changed because storing zero to mem is an integer instruction not an FP instruction. Testing showed that we have testcases for float/double 0, but the testcases are a little confused as they are storing 0 to mem and expecting to see an fmov instruction. I split the testcases into two, so we can have a 0 to reg case that expects fmov, and a 0 to mem case that expects str of the zero reg. I also added the equivalent missing long double testcases. This was tested with a default languages make bootstrap and make check.. I see an additional 8 passes, and no other change in the testsuite results. Jim gcc/ 2015-06-19 Jim Wilson * config/aarch64/aarch64.md (mov:GPF): Don't call force_reg if op1 is an fp zero. (movsf_aarch64): Change condition from register_operand to aarch64_reg_or_fp_zero for op1. Change type for alternative 6 to load1. Change type for alternative 7 to store1. (movdf_aarch64): Likewise. gcc/testsuite/ 2015-06-19 Jim Wilson * gcc.target/aarch64/fmovd-zero-mem.c: New. * gcc.target/aarch64/fmovd-zero-reg.c: New. * gcc.target/aarch64/fmovf-zero-mem.c: New. * gcc.target/aarch64/fmovf-zero-reg.c: New. * gcc.target/aarch64/fmovld-zero-mem.c: New. * gcc.target/aarch64/fmovld-zero-mem.c: New. * gcc.target/aarch64/fmovd-zero.c: Delete. * gcc.target/aarch64/fmovf-zero.c: Delete. Index: config/aarch64/aarch64.md =================================================================== --- config/aarch64/aarch64.md (revision 224493) +++ config/aarch64/aarch64.md (working copy) @@ -986,7 +986,9 @@ (define_expand "mov" FAIL; } - if (GET_CODE (operands[0]) == MEM) + if (GET_CODE (operands[0]) == MEM + && ! (GET_CODE (operands[1]) == CONST_DOUBLE + && aarch64_float_const_zero_rtx_p (operands[1]))) operands[1] = force_reg (mode, operands[1]); " ) @@ -995,7 +997,7 @@ (define_insn "*movsf_aarch64" [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode))" + || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ fmov\\t%s0, %w1 fmov\\t%w0, %s1 @@ -1007,14 +1009,14 @@ (define_insn "*movsf_aarch64" str\\t%w1, %0 mov\\t%w0, %w1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,f_loads,f_stores,mov_reg")] + f_loads,f_stores,load1,store1,mov_reg")] ) (define_insn "*movdf_aarch64" [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ fmov\\t%d0, %x1 fmov\\t%x0, %d1 @@ -1026,7 +1028,7 @@ (define_insn "*movdf_aarch64" str\\t%x1, %0 mov\\t%x0, %x1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,f_loadd,f_stored,mov_reg")] + f_loadd,f_stored,load1,store1,mov_reg")] ) (define_expand "movtf" Index: testsuite/gcc.target/aarch64/fmovd-zero-mem.c =================================================================== --- testsuite/gcc.target/aarch64/fmovd-zero-mem.c (revision 0) +++ testsuite/gcc.target/aarch64/fmovd-zero-mem.c (working copy) @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +foo (double *output) +{ + *output = 0.0; +} + +/* { dg-final { scan-assembler "str\\txzr, \\\[x0\\\]" } } */ Index: testsuite/gcc.target/aarch64/fmovd-zero-reg.c =================================================================== --- testsuite/gcc.target/aarch64/fmovd-zero-reg.c (revision 0) +++ testsuite/gcc.target/aarch64/fmovd-zero-reg.c (working copy) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (double); +void +foo (void) +{ + bar (0.0); +} + +/* { dg-final { scan-assembler "fmov\\td0, xzr" } } */ Index: testsuite/gcc.target/aarch64/fmovd-zero.c =================================================================== --- testsuite/gcc.target/aarch64/fmovd-zero.c (revision 224493) +++ testsuite/gcc.target/aarch64/fmovd-zero.c (working copy) @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2" } */ - -void -foo (double *output) -{ - *output = 0.0; -} - -/* { dg-final { scan-assembler "fmov\\td\[0-9\]+, xzr" } } */ Index: testsuite/gcc.target/aarch64/fmovf-zero-mem.c =================================================================== --- testsuite/gcc.target/aarch64/fmovf-zero-mem.c (revision 0) +++ testsuite/gcc.target/aarch64/fmovf-zero-mem.c (working copy) @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +foo (float *output) +{ + *output = 0.0; +} + +/* { dg-final { scan-assembler "str\\twzr, \\\[x0\\\]" } } */ Index: testsuite/gcc.target/aarch64/fmovf-zero-reg.c =================================================================== --- testsuite/gcc.target/aarch64/fmovf-zero-reg.c (revision 0) +++ testsuite/gcc.target/aarch64/fmovf-zero-reg.c (working copy) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (float); +void +foo (void) +{ + bar (0.0); +} + +/* { dg-final { scan-assembler "fmov\\ts0, wzr" } } */ Index: testsuite/gcc.target/aarch64/fmovf-zero.c =================================================================== --- testsuite/gcc.target/aarch64/fmovf-zero.c (revision 224493) +++ testsuite/gcc.target/aarch64/fmovf-zero.c (working copy) @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2" } */ - -void -foo (float *output) -{ - *output = 0.0; -} - -/* { dg-final { scan-assembler "fmov\\ts\[0-9\]+, wzr" } } */ Index: testsuite/gcc.target/aarch64/fmovld-zero-mem.c =================================================================== --- testsuite/gcc.target/aarch64/fmovld-zero-mem.c (revision 0) +++ testsuite/gcc.target/aarch64/fmovld-zero-mem.c (working copy) @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +foo (long double *output) +{ + *output = 0.0; +} + +/* { dg-final { scan-assembler "stp\\txzr, xzr, \\\[x0\\\]" } } */ Index: testsuite/gcc.target/aarch64/fmovld-zero-reg.c =================================================================== --- testsuite/gcc.target/aarch64/fmovld-zero-reg.c (revision 0) +++ testsuite/gcc.target/aarch64/fmovld-zero-reg.c (working copy) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (long double); +void +foo (void) +{ + bar (0.0); +} + +/* { dg-final { scan-assembler "movi\\tv0\.2d, #0" } } */