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Fri, 09 Dec 2016 03:28:28 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com (10.166.214.7) by CY1PR07MB2314.namprd07.prod.outlook.com (10.166.194.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.771.8; Fri, 9 Dec 2016 03:28:25 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) by CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) with mapi id 15.01.0771.010; Fri, 9 Dec 2016 03:28:24 +0000 From: "Hurugalawadi, Naveen" To: "gcc-patches@gcc.gnu.org" CC: "Pinski, Andrew" , James Greenhalgh , Marcus Shawcroft , Richard Earnshaw Subject: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion Date: Fri, 9 Dec 2016 03:28:24 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Naveen.Hurugalawadi@cavium.com; x-microsoft-exchange-diagnostics: 1; CY1PR07MB2314; 7:ndfdrDYNWGjDdnK8hzRBLWShob/GsOFzLBHU/+HQaKd/vR6b+fUc+/gbJ2xeJ53P2wvYnyVVYZ7SIJ1ww8U6NhdhkqlCxMFd1npn/RcRZhVAcP7qDXh3+8PjLP8nviSZYgAFnl/8/+7ESLmr9n9qF3O3BYKN98FXu4+8EZ/NTfJxXM+/SoQFjsV2+3Oz8ehf0QzxbVeVTqMOE57vSI+aoPxrbdrdvyzYn2sLUbe2kjs+/tzyGYJqm+fWdBu0gQohcfRmxMDRUwKlbuEcT+4NEWe1AabRq7IbV/Xflg06jcb1ZLr7mCFDDrRJQWy1MwFL1mbZkKx9588oEf5y3tJWhJ7G4Um6Fki0ox0WRpiZtiQuY4wos4MYeDQHFRu2jsFYESb2/68fYu9erHbvzW3+bCX3PQCdceztAL85ohig9+zXNyvQyqMoUhMmU/ZhsbXZOE+gz5VYge9PN1hO/schvw== x-forefront-antispam-report: SFV:SKI; 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PCL:0; RULEID:(102415395)(6040375)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6041248)(20161123562025)(20161123555025)(20161123564025)(20161123560025)(20161123558021)(6072148); SRVR:CY1PR07MB2314; BCL:0; PCL:0; RULEID:; SRVR:CY1PR07MB2314; x-forefront-prvs: 015114592F received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Dec 2016 03:28:24.6018 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR07MB2314 Hi, The AArch64 vector initialization sequence can be optimized to generate better code. The attached patch handles for the case where the vector contains only variables. It checks for the common elements in the vector and inserts the values in optimized way. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay? 2016-12-09 Andrew PInski gcc * config/aarch64/aarch64.c (aarch64_expand_vector_init): Improve vector initialization code gen. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e87831f..da5b6fa 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11609,11 +11609,54 @@ aarch64_expand_vector_init (rtx target, rtx vals) aarch64_expand_vector_init (target, copy); } - /* Insert the variable lanes directly. */ - enum insn_code icode = optab_handler (vec_set_optab, mode); gcc_assert (icode != CODE_FOR_nothing); + /* If there is only varables, try to optimize + the inseration using dup for the most common element + followed by insertations. */ + if (n_var == n_elts && n_elts <= 16) + { + int matches[16][2]; + int nummatches = 0; + memset (matches, 0, sizeof(matches)); + for(int i = 0; i < n_elts; i++) + { + for (int j = 0; j <= i; j++) + { + if (rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, j))) + { + matches[i][0] = j; + matches[j][1]++; + if (i != j) + nummatches++; + break; + } + } + } + int maxelement = 0; + int maxv = 0; + for (int i = 0; i < n_elts; i++) + if (matches[i][1] > maxv) + maxelement = i, maxv = matches[i][1]; + + /* Create a duplicate of the most common element. */ + rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement)); + aarch64_emit_move (target, gen_rtx_VEC_DUPLICATE (mode, x)); + /* Insert the rest. */ + for (int i = 0; i < n_elts; i++) + { + rtx x = XVECEXP (vals, 0, i); + if (matches[i][0] == maxelement) + continue; + x = copy_to_mode_reg (inner_mode, x); + emit_insn (GEN_FCN (icode) (target, x, GEN_INT (i))); + } + return; + } + + /* Insert the variable lanes directly. */ + for (int i = 0; i < n_elts; i++) { rtx x = XVECEXP (vals, 0, i);