From patchwork Tue Nov 8 13:36:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 81320 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp1551460qge; Tue, 8 Nov 2016 05:37:05 -0800 (PST) X-Received: by 10.99.106.200 with SMTP id f191mr18942692pgc.143.1478612225637; Tue, 08 Nov 2016 05:37:05 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id fk6si15124086pac.133.2016.11.08.05.37.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Nov 2016 05:37:05 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-440750-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-440750-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-440750-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=w28g6NmeykB5kCw5W oG63tOLq8CaTI22e2pspSju4mnpoWHk280T+JC2W85Q0fqxxC8d/uwR3VZNTwREn SR+aYOanWhtmhGZiKCxW2jgP8GlLg+HCAWtVB/J8u9HFhXAth3lwj9HR2lXthVo6 eNVtEjKI8Uvf397WqCV5+GbUyA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=BHGY+QMBbu20vS/GPLCfHiU OCf4=; b=qNw1xEX4rKYZ6SKJE5XSa/83AFsydfonKen1lNoI+4UvdXPeYgGFe6d kiS03yZA2T3bNcZvT9rwtoNgd0/1M7gLbUQrBZ/4JVEeeH/bYsAngPFtzHx2t+sv 7lLTIQbcQen1+J6yj02Q8iQ2WOrFB705DvAyQzr3CvGt/AV2v2t8= Received: (qmail 101699 invoked by alias); 8 Nov 2016 13:36:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 101674 invoked by uid 89); 8 Nov 2016 13:36:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.5 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=aims, @tab, 1174, alongside X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 08 Nov 2016 13:36:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3EB3513D9; Tue, 8 Nov 2016 05:36:34 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4DCFC3F25D; Tue, 8 Nov 2016 05:36:33 -0800 (PST) Subject: Re: [PATCH, GCC/ARM 1/2, ping2] Add multilib support for embedded bare-metal targets To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <24a10c3b-c98f-b3b6-d60a-bf0a6fd1b5bf@foss.arm.com> <5811CCCB.9010302@foss.arm.com> <4981b2dc-334e-8ed5-0659-98d3fdd3d7dc@foss.arm.com> <2bcfb596-1c2f-988a-ddd3-64e56fcf54af@foss.arm.com> Cc: "Jasmin J." From: Thomas Preudhomme Message-ID: Date: Tue, 8 Nov 2016 13:36:32 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <2bcfb596-1c2f-988a-ddd3-64e56fcf54af@foss.arm.com> X-IsSubscribed: yes Ping? Best regards, Thomas On 02/11/16 10:05, Thomas Preudhomme wrote: > Ping? > > Best regards, > > Thomas > > On 27/10/16 15:26, Thomas Preudhomme wrote: >> Hi Kyrill, >> >> On 27/10/16 10:45, Kyrill Tkachov wrote: >>> Hi Thomas, >>> >>> On 24/10/16 09:06, Thomas Preudhomme wrote: >>>> Ping? >>>> >>>> Best regards, >>>> >>>> Thomas >>>> >>>> On 13/10/16 16:35, Thomas Preudhomme wrote: >>>>> Hi ARM maintainers, >>>>> >>>>> This patchset aims at adding multilib support for R and M profile ARM >>>>> architectures and allowing it to be built alongside multilib for A profile ARM >>>>> architectures. This specific patch adds the t-rmprofile multilib Makefile >>>>> fragment for the former objective. Multilib are built for all M profile >>>>> architecture involved: ARMv6S-M, ARMv7-M and ARMv7E-M as well as ARMv7. ARMv7 >>>>> multilib is used for R profile architectures but also A profile architectures. >>>>> >>>>> ChangeLog entry is as follows: >>>>> >>>>> >>>>> *** gcc/ChangeLog *** >>>>> >>>>> 2016-10-03 Thomas Preud'homme >>>>> >>>>> * config.gcc: Allow new rmprofile value for configure option >>>>> --with-multilib-list. >>>>> * config/arm/t-rmprofile: New file. >>>>> * doc/install.texi (--with-multilib-list): Document new rmprofile >>>>> value >>>>> for ARM. >>>>> >>>>> >>>>> Testing: >>>>> >>>>> == aprofile == >>>>> * "tree install/lib/gcc/arm-none-eabi/7.0.0" is the same before and after the >>>>> patchset for both aprofile and rmprofile >>>>> * default spec (gcc -dumpspecs) is the same before and after the patchset for >>>>> aprofile >>>>> * No difference in --print-multi-directory between before and after the >>>>> patchset >>>>> for aprofile for all combination of ISA (ARM/Thumb), architecture, CPU, FPU >>>>> and >>>>> float ABI >>>>> >>>>> == rmprofile == >>>>> * aprofile and rmprofile use similar directory structure (ISA/arch/FPU/float >>>>> ABI) and directory naming >>>>> * Difference in --print-multi-directory between before [1] and after the >>>>> patchset for rmprofile for all combination of ISA (ARM/Thumb), architecture, >>>>> CPU, FPU and float ABI modulo the name and directory structure changes >>>>> >>>>> [1] as per patch applied in ARM embedded branches >>>>> https://gcc.gnu.org/viewcvs/gcc/branches/ARM/embedded-5-branch/gcc/config/arm/t-baremetal?view=markup >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> == aprofile + rmprofile == >>>>> * aprofile,rmprofile and rmprofile,aprofile builds give an error saying it is >>>>> not supported >>>>> >>>>> >>>>> Is this ok for master branch? >>>>> >>>>> Best regards, >>>>> >>>>> Thomas >>> >>> +# Arch Matches >>> +MULTILIB_MATCHES += march?armv6s-m=march?armv6-m >>> +MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp >>> +MULTILIB_MATCHES += march?armv7=march?armv7-r >>> +ifeq (,$(HAS_APROFILE)) >>> +MULTILIB_MATCHES += march?armv7=march?armv7-a >>> +MULTILIB_MATCHES += march?armv7=march?armv7ve >>> +MULTILIB_MATCHES += march?armv7=march?armv8-a >>> +MULTILIB_MATCHES += march?armv7=march?armv8-a+crc >>> +MULTILIB_MATCHES += march?armv7=march?armv8.1-a >>> +MULTILIB_MATCHES += march?armv7=march?armv8.1-a+crc >>> +endif >>> >>> I think you want to update the patch to handle -march=armv8.2-a and >>> armv8.2-a+fp16 >>> Thanks, >>> Kyrill >> >> Indeed. Please find updated ChangeLog and patch (attached): >> >> *** gcc/ChangeLog *** >> >> 2016-10-03 Thomas Preud'homme >> >> * config.gcc: Allow new rmprofile value for configure option >> --with-multilib-list. >> * config/arm/t-rmprofile: New file. >> * doc/install.texi (--with-multilib-list): Document new rmprofile value >> for ARM. >> >> Ok for trunk? >> >> Best regards, >> >> Thomas diff --git a/gcc/config.gcc b/gcc/config.gcc index d956da22ad60abfe9c6b4be0882f9e7dd64ac39f..15b662ad5449f8b91eb760b7fbe45f33d8cecb4b 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3739,6 +3739,16 @@ case "${target}" in # pragmatic. tmake_profile_file="arm/t-aprofile" ;; + rmprofile) + # Note that arm/t-rmprofile is a + # stand-alone make file fragment to be + # used only with itself. We do not + # specifically use the + # TM_MULTILIB_OPTION framework because + # this shorthand is more + # pragmatic. + tmake_profile_file="arm/t-rmprofile" + ;; default) ;; *) @@ -3748,9 +3758,10 @@ case "${target}" in esac if test "x${tmake_profile_file}" != x ; then - # arm/t-aprofile is only designed to work - # without any with-cpu, with-arch, with-mode, - # with-fpu or with-float options. + # arm/t-aprofile and arm/t-rmprofile are only + # designed to work without any with-cpu, + # with-arch, with-mode, with-fpu or with-float + # options. if test "x$with_arch" != x \ || test "x$with_cpu" != x \ || test "x$with_float" != x \ diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile new file mode 100644 index 0000000000000000000000000000000000000000..c8b5c9cbd03694eea69855e20372afa3e97d6b4c --- /dev/null +++ b/gcc/config/arm/t-rmprofile @@ -0,0 +1,174 @@ +# Copyright (C) 2016 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# This is a target makefile fragment that attempts to get +# multilibs built for the range of CPU's, FPU's and ABI's that +# are relevant for the ARM architecture. It should not be used in +# conjunction with another make file fragment and assumes --with-arch, +# --with-cpu, --with-fpu, --with-float, --with-mode have their default +# values during the configure step. We enforce this during the +# top-level configury. + +MULTILIB_OPTIONS = +MULTILIB_DIRNAMES = +MULTILIB_EXCEPTIONS = +MULTILIB_MATCHES = +MULTILIB_REUSE = + +# We have the following hierachy: +# ISA: A32 (.) or T16/T32 (thumb). +# Architecture: ARMv6S-M (v6-m), ARMv7-M (v7-m), ARMv7E-M (v7e-m), +# ARMv8-M Baseline (v8-m.base) or ARMv8-M Mainline (v8-m.main). +# FPU: VFPv3-D16 (fpv3), FPV4-SP-D16 (fpv4-sp), FPV5-SP-D16 (fpv5-sp), +# VFPv5-D16 (fpv5), or None (.). +# Float-abi: Soft (.), softfp (softfp), or hard (hardfp). + +# Options to build libraries with + +MULTILIB_OPTIONS += mthumb +MULTILIB_DIRNAMES += thumb + +MULTILIB_OPTIONS += march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7/march=armv8-m.base/march=armv8-m.main +MULTILIB_DIRNAMES += v6-m v7-m v7e-m v7-ar v8-m.base v8-m.main + +MULTILIB_OPTIONS += mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-sp-d16/mfpu=fpv5-d16 +MULTILIB_DIRNAMES += fpv3 fpv4-sp fpv5-sp fpv5 + +MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard +MULTILIB_DIRNAMES += softfp hard + + +# Option combinations to build library with + +# Default CPU/Arch +MULTILIB_REQUIRED += mthumb +MULTILIB_REQUIRED += mfloat-abi=hard + +# ARMv6-M +MULTILIB_REQUIRED += mthumb/march=armv6s-m + +# ARMv8-M Baseline +MULTILIB_REQUIRED += mthumb/march=armv8-m.base + +# ARMv7-M +MULTILIB_REQUIRED += mthumb/march=armv7-m + +# ARMv7E-M +MULTILIB_REQUIRED += mthumb/march=armv7e-m +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=hard + +# ARMv8-M Mainline +MULTILIB_REQUIRED += mthumb/march=armv8-m.main +MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=hard + +# ARMv7-R as well as ARMv7-A and ARMv8-A if aprofile was not specified +MULTILIB_REQUIRED += mthumb/march=armv7 +MULTILIB_REQUIRED += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=hard + + +# Matches + +# CPU Matches +MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0 +MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0.small-multiply +MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0plus +MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0plus.small-multiply +MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m1 +MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m1.small-multiply +MULTILIB_MATCHES += march?armv7-m=mcpu?cortex-m3 +MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m4 +MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m7 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f +MULTILIB_MATCHES += march?armv7=mcpu?cortex-r5 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-r7 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-r8 +MULTILIB_MATCHES += march?armv7=mcpu?marvell-pj4 +MULTILIB_MATCHES += march?armv7=mcpu?generic-armv7-a +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a5 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a7 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a12 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a17 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15.cortex-a7 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a17.cortex-a7 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a32 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a35 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a53 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a57 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a57.cortex-a53 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a72 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a72.cortex-a53 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a35 +MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a53 +MULTILIB_MATCHES += march?armv7=mcpu?exynos-m1 +MULTILIB_MATCHES += march?armv7=mcpu?qdf24xx +MULTILIB_MATCHES += march?armv7=mcpu?xgene1 + +# Arch Matches +MULTILIB_MATCHES += march?armv6s-m=march?armv6-m +MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp +MULTILIB_MATCHES += march?armv7=march?armv7-r +ifeq (,$(HAS_APROFILE)) +MULTILIB_MATCHES += march?armv7=march?armv7-a +MULTILIB_MATCHES += march?armv7=march?armv7ve +MULTILIB_MATCHES += march?armv7=march?armv8-a +MULTILIB_MATCHES += march?armv7=march?armv8-a+crc +MULTILIB_MATCHES += march?armv7=march?armv8.1-a +MULTILIB_MATCHES += march?armv7=march?armv8.1-a+crc +MULTILIB_MATCHES += march?armv7=march?armv8.2-a +MULTILIB_MATCHES += march?armv7=march?armv8.2-a+fp16 +endif + +# FPU matches +ifeq (,$(HAS_APROFILE)) +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3 +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16 +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16 +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-fp16 +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4 +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4-d16 +MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-vfpv4 +MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?fp-armv8 +MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?neon-fp-armv8 +MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?crypto-neon-fp-armv8 +endif + + +# We map all requests for ARMv7-R or ARMv7-A in ARM mode to Thumb mode and +# any FPU to VFPv3-d16 if possible. +MULTILIB_REUSE += mthumb/march.armv7=march.armv7 +MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp +MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard +MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp +MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.fpv5-d16/mfloat-abi.hard +MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp +MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.hard diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index e4c686e60c7f479ca3ea71e94c4bb6ad52373085..0b94bc1931a226e58d06a7ed5a726454142c006a 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1107,19 +1107,59 @@ sysv, aix. @item --with-multilib-list=@var{list} @itemx --without-multilib-list -Specify what multilibs to build. -Currently only implemented for arm*-*-*, sh*-*-* and x86-64-*-linux*. +Specify what multilibs to build. @var{list} is a comma separated list of +values, possibly consisting of a single value. Currently only implemented +for arm*-*-*, sh*-*-* and x86-64-*-linux*. The accepted values and meaning +for each target is given below. @table @code @item arm*-*-* -@var{list} is either @code{default} or @code{aprofile}. Specifying -@code{default} is equivalent to omitting this option while specifying -@code{aprofile} builds multilibs for each combination of ISA (@code{-marm} or -@code{-mthumb}), architecture (@code{-march=armv7-a}, @code{-march=armv7ve}, -or @code{-march=armv8-a}), FPU available (none, @code{-mfpu=vfpv3-d16}, -@code{-mfpu=neon}, @code{-mfpu=vfpv4-d16}, @code{-mfpu=neon-vfpv4} or -@code{-mfpu=neon-fp-armv8} depending on architecture) and floating-point ABI -(@code{-mfloat-abi=softfp} or @code{-mfloat-abi=hard}). +@var{list} is one of@code{default}, @code{aprofile} or @code{rmprofile}. +Specifying @code{default} is equivalent to omitting this option, ie. only the +default runtime library will be enabled. Specifying @code{aprofile} or +@code{rmprofile} builds multilibs for a combination of ISA, architecture, +FPU available and floating-point ABI. + +The table below gives the combination of ISAs, architectures, FPUs and +floating-point ABIs for which multilibs are built for each accepted value. + +@multitable @columnfractions .15 .28 .30 +@item Option @tab aprofile @tab rmprofile +@item ISAs +@tab @code{-marm} and @code{-mthumb} +@tab @code{-mthumb} +@item Architectures@*@*@*@*@*@* +@tab default architecture@* +@code{-march=armv7-a}@* +@code{-march=armv7ve}@* +@code{-march=armv8-a}@*@*@* +@tab default architecture@* +@code{-march=armv6s-m}@* +@code{-march=armv7-m}@* +@code{-march=armv7e-m}@* +@code{-march=armv8-m.base}@* +@code{-march=armv8-m.main}@* +@code{-march=armv7} +@item FPUs@*@*@*@*@* +@tab none@* +@code{-mfpu=vfpv3-d16}@* +@code{-mfpu=neon}@* +@code{-mfpu=vfpv4-d16}@* +@code{-mfpu=neon-vfpv4}@* +@code{-mfpu=neon-fp-armv8} +@tab none@* +@code{-mfpu=vfpv3-d16}@* +@code{-mfpu=fpv4-sp-d16}@* +@code{-mfpu=fpv5-sp-d16}@* +@code{-mfpu=fpv5-d16}@* +@item floating-point@/ ABIs@*@* +@tab @code{-mfloat-abi=soft}@* +@code{-mfloat-abi=softfp}@* +@code{-mfloat-abi=hard} +@tab @code{-mfloat-abi=soft}@* +@code{-mfloat-abi=softfp}@* +@code{-mfloat-abi=hard} +@end multitable @item sh*-*-* @var{list} is a comma separated list of CPU names. These must be of the