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[209.132.180.131]) by mx.google.com with ESMTPS id a2si958984plt.408.2017.06.09.06.04.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Jun 2017 06:04:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-455544-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-455544-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-455544-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=XBPI5C2YQlGE1CQs8PAvOlSsxqS5+VRN8URGYnsG8Z4vUwIXrvtPt tGFDLK+8tub9XKX35JepXnQhtO2ZZ8OESk3O6FgELFIcBM/YhesCEb3muw4cw3+O 0l3BI5UEmsPxD18oNW0/xWEA77GOQeD3B0AEdDTONzfzkepweNuyIY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; s=default; bh=a/VTytH7ZIp1TPc1FMs+D8kpBEY=; b=s9Kj5q/NM6JMuAanMTasRo6bhgPk w86YcIbXjmQ9dgvuK+seVB3BbJ6d/gmnuwGHk4v+9KLQhhU8VzTzU/4L8cHxvH1t 3ZL6apELIBuUyTHX36vkhXHH1iZewoXu6xhZ7S3Nd6QX8B2ihQxig7ZiGTjaMI2H 0YfMLClo6YUFpoY= Received: (qmail 100355 invoked by alias); 9 Jun 2017 12:55:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 89628 invoked by uid 89); 9 Jun 2017 12:54:46 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 12:54:38 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJJQn-0007fc-Lg for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:30 -0400 Received: from foss.arm.com ([217.140.101.70]:47128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJJQn-0007Te-5P for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:25 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D49A12B; Fri, 9 Jun 2017 05:54:24 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5BBA53F3E1; Fri, 9 Jun 2017 05:54:24 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 22/30] [arm] Rewrite t-rmprofile multilib specification Date: Fri, 9 Jun 2017 13:53:51 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 This is the R- & M-profile equivalent of the previous A-profile multilib rewrite. Additionally this patch adds some top-level rules to help find suitable multilibs for general cases when certain libraries are not built, or when building for legacy cores. gcc: * config/arm/t-aprofile (v7_a_nosimd_variants, v7_a_simd_variants) (v7ve_nosimd_variatns, v7ve_vfpv3_simd_variants) (v7ve_vfpv4_simd_variants, v8_a_nosimd_variants, v8_a_simd_variants) (v8_1_a_simd_variants, v8_2_a_simd_variants): Move to ... * config/arm/t-multilib: ... here. (MULTILIB_OPTIONS): Add armv7 and armv7+fp architectures. (MULTILIB_MATCHES): Use armv7 libraries for armv7-r. Also use for armv7-a and armv8*-a when A-profile libraries have not been built. * config/arm/t-rmprofile: Rewrite. gcc/testsuite: * gcc.target/arm/multilib.exp (rmprofile): New tests when rm-profile multilibs have been built. --- gcc/config/arm/t-aprofile | 13 -- gcc/config/arm/t-multilib | 96 +++++++++- gcc/config/arm/t-rmprofile | 147 +++------------ gcc/testsuite/gcc.target/arm/multilib.exp | 304 ++++++++++++++++++++++++++++++ 4 files changed, 421 insertions(+), 139 deletions(-) diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index 2e3d4c8..0a36d05 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -24,19 +24,6 @@ # have their default values during the configure step. We enforce # this during the top-level configury. -# Variables used later in this file. - -v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4 -v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4 -v7ve_nosimd_variants := +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +fp +vfpv4 -v7ve_vfpv3_simd_variants := +neon +neon-fp16 -v7ve_vfpv4_simd_variants := +simd -v8_a_nosimd_variants := +crc -v8_a_simd_variants := $(call all_feat_combs, simd crypto) -v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) -v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) - - # Arch and FPU variants to build libraries with MULTI_ARCH_OPTS_A = march=armv7-a/march=armv7-a+fp/march=armv7-a+simd/march=armv7ve+simd/march=armv8-a/march=armv8-a+simd diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 77ce762..ec4b76d 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -57,6 +57,20 @@ all_feat_combs = +$(firstword $(1)) \ $(wordlist 2, $(words $(1)), $(1))), \ +$(firstword $(1))$(OPT) $(OPT)),) +# Variables used. +all_early_arch := armv5e armv5tej armv6 armv6j armv6k armv6z armv6kz \ + armv6zk armv6t2 iwmmxt iwmmxt2 +v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4 +v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4 +v7ve_nosimd_variants := +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +fp +vfpv4 +v7ve_vfpv3_simd_variants := +neon +neon-fp16 +v7ve_vfpv4_simd_variants := +simd +v8_a_nosimd_variants := +crc +v8_a_simd_variants := $(call all_feat_combs, simd crypto) +v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) +v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) + + ifneq (,$(HAS_APROFILE)) include $(srcdir)/config/arm/t-aprofile endif @@ -66,14 +80,80 @@ endif SEP := $(and $(HAS_APROFILE),$(HAS_RMPROFILE),/) -MULTILIB_OPTIONS += marm/mthumb -MULTILIB_DIRNAMES += arm thumb +MULTILIB_OPTIONS += marm/mthumb +MULTILIB_DIRNAMES += arm thumb + +MULTILIB_OPTIONS += march=armv5te+fp/march=armv7/march=armv7+fp/$(MULTI_ARCH_OPTS_A)$(SEP)$(MULTI_ARCH_OPTS_RM) +MULTILIB_DIRNAMES += v5te v7 v7+fp $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) + +MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=softfp/mfloat-abi=hard +MULTILIB_DIRNAMES += nofp softfp hard + +MULTILIB_REQUIRED += mthumb/mfloat-abi=soft +MULTILIB_REQUIRED += marm/march=armv5te+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += marm/march=armv5te+fp/mfloat-abi=hard + +MULTILIB_REQUIRED += mthumb/march=armv7/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv7+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7+fp/mfloat-abi=hard + +# Map v7-r down onto common v7 code. +MULTILIB_MATCHES += march?armv7=march?armv7-r +MULTILIB_MATCHES += march?armv7=march?armv7-r+idiv +MULTILIB_MATCHES += march?armv7+fp=march?armv7-r+fp +MULTILIB_MATCHES += march?armv7+fp=march?armv7-r+fp+idiv + +MULTILIB_MATCHES += $(foreach ARCH, $(all_early_arch), \ + march?armv5te+fp=march?$(ARCH)+fp) + +ifeq (,$(HAS_APROFILE)) +# Map all v7-a +MULTILIB_MATCHES += march?armv7=march?armv7-a +MULTILIB_MATCHES += $(foreach ARCH, $(v7_a_nosimd_variants) $(v7_a_simd_variants), \ + march?armv7+fp=march?armv7-a$(ARCH)) + +MULTILIB_MATCHES += march?armv7=march?armv7ve + +# ARMv7ve FP/SIMD variants: map down to v7+fp +MULTILIB_MATCHES += $(foreach ARCH, $(v7ve_nosimd_variants) $(v7ve_vfpv3_simd_variants) $(v7ve_vfpv4_simd_variants), \ + march?armv7+fp=march?armv7ve$(ARCH)) + +# ARMv8 +MULTILIB_MATCHES += march?armv7=march?armv8-a +MULTILIB_MATCHES += $(foreach ARCH, $(v8_a_nosimd_variants), \ + march?armv7=march?armv8-a$(ARCH)) + +# ARMv8 with SIMD +MULTILIB_MATCHES += march?armv7+fp=march?armv8-a+crc+simd \ + $(foreach ARCH, $(v8_a_simd_variants), \ + march?armv7+fp=march?armv8-a$(ARCH) \ + march?armv7+fp=march?armv8-a+crc$(ARCH)) + +# Baseline v8.1-a +MULTILIB_MATCHES += march?armv7=march?armv8.1-a + +# Map all v8.1-a SIMD variants +MULTILIB_MATCHES += $(foreach ARCH, $(v8_1_a_simd_variants), \ + march?armv7+fp=march?armv8.1-a$(ARCH)) + +# Baseline v8.2-a: map down to baseline v8-a +MULTILIB_MATCHES += march?armv7=march?armv8.2-a + +# Map all v8.2-a SIMD variants +MULTILIB_MATCHES += $(foreach ARCH, $(v8_2_a_simd_variants), \ + march?armv7+fp=march?armv8.2-a$(ARCH)) + +# Use Thumb libraries for everything. + +MULTILIB_REUSE += mthumb/march.armv7/mfloat-abi.soft=marm/march.armv7/mfloat-abi.soft -MULTILIB_OPTIONS += march=armv5te+fp/$(MULTI_ARCH_OPTS_A)$(SEP)$(MULTI_ARCH_OPTS_RM) -MULTILIB_DIRNAMES += v5te $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) +MULTILIB_REUSE += $(foreach ABI, hard softfp, \ + $(foreach ARCH, armv7+fp, \ + mthumb/march.$(ARCH)/mfloat-abi.$(ABI)=marm/march.$(ARCH)/mfloat-abi.$(ABI))) -MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=softfp/mfloat-abi=hard -MULTILIB_DIRNAMES += nofp softfp hard +# Softfp but no FP, use the soft-float libraries. +MULTILIB_REUSE += $(foreach MODE, arm thumb, \ + $(foreach ARCH, armv7, \ + mthumb/march.$(ARCH)/mfloat-abi.soft=m$(MODE)/march.$(ARCH)/mfloat-abi.softfp)) -MULTILIB_REQUIRED += mthumb/mfloat-abi=soft -MULTILIB_REQUIRED += marm/march=armv5te+fp/mfloat-abi=hard +endif # Not APROFILE. \ No newline at end of file diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile index 8cd7351..1ad8eac 100644 --- a/gcc/config/arm/t-rmprofile +++ b/gcc/config/arm/t-rmprofile @@ -27,131 +27,42 @@ # Arch and FPU variants to build libraries with -MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7/march=armv8-m.base/march=armv8-m.main -MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7-ar v8-m.base v8-m.main +MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp +MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp -MULTI_FPU_OPTS_RM = mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-sp-d16/mfpu=fpv5-d16 -MULTI_FPU_DIRS_RM = fpv3 fpv4-sp fpv5-sp fpv5 +# Base M-profile (no fp) +MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfloat-abi=soft +# ARMv7e-M with FP (single and double precision variants) +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=softfp -# Option combinations to build library with +# ARMv8-M with FP (single and double precision variants) +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=softfp -# Default CPU/Arch -MULTILIB_REQUIRED += mthumb -MULTILIB_REQUIRED += mfloat-abi=hard -# ARMv6-M -MULTILIB_REQUIRED += mthumb/march=armv6s-m - -# ARMv8-M Baseline -MULTILIB_REQUIRED += mthumb/march=armv8-m.base - -# ARMv7-M -MULTILIB_REQUIRED += mthumb/march=armv7-m - -# ARMv7E-M -MULTILIB_REQUIRED += mthumb/march=armv7e-m -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=hard - -# ARMv8-M Mainline -MULTILIB_REQUIRED += mthumb/march=armv8-m.main -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=hard - -# ARMv7-R as well as ARMv7-A and ARMv8-A if aprofile was not specified -MULTILIB_REQUIRED += mthumb/march=armv7 -MULTILIB_REQUIRED += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=hard - - -# Matches - -# CPU Matches -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0 -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0.small-multiply -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0plus -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0plus.small-multiply -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m1 -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m1.small-multiply -MULTILIB_MATCHES += march?armv7-m=mcpu?cortex-m3 -MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m4 -MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m7 -MULTILIB_MATCHES += march?armv8-m.base=mcpu?cortex-m23 -MULTILIB_MATCHES += march?armv8-m.main=mcpu?cortex-m33 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r5 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r8 -MULTILIB_MATCHES += march?armv7=mcpu?marvell-pj4 -MULTILIB_MATCHES += march?armv7=mcpu?generic-armv7-a -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a5 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a12 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a17 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15.cortex-a7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a17.cortex-a7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a32 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a35 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a57 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a57.cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a72 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a72.cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a35 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?exynos-m1 -MULTILIB_MATCHES += march?armv7=mcpu?qdf24xx -MULTILIB_MATCHES += march?armv7=mcpu?xgene1 # Arch Matches -MULTILIB_MATCHES += march?armv6s-m=march?armv6-m -MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp -MULTILIB_MATCHES += march?armv7=march?armv7-r -ifeq (,$(HAS_APROFILE)) -MULTILIB_MATCHES += march?armv7=march?armv7-a -MULTILIB_MATCHES += march?armv7=march?armv7ve -MULTILIB_MATCHES += march?armv7=march?armv8-a -MULTILIB_MATCHES += march?armv7=march?armv8-a+crc -MULTILIB_MATCHES += march?armv7=march?armv8.1-a -MULTILIB_MATCHES += march?armv7=march?armv8.1-a+crc -MULTILIB_MATCHES += march?armv7=march?armv8.2-a -MULTILIB_MATCHES += march?armv7=march?armv8.2-a+fp16 -endif +MULTILIB_MATCHES += march?armv6s-m=march?armv6-m + +# Map all v8-m.main+dsp FP variants down the the variant without DSP. +MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp \ + $(foreach FP, +fp +fp.dp, \ + march?armv8-m.main$(FP)=march?armv8-m.main+dsp$(FP)) -# FPU matches -ifeq (,$(HAS_APROFILE)) -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-fp16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4-d16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-vfpv4 -MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?fp-armv8 -MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?neon-fp-armv8 -MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?crypto-neon-fp-armv8 -endif +# For single-precision only fpv5, use the base fp libraries +MULTILIB_MATCHES += march?armv7e-m+fp=march?armv7e-m+fpv5 +# Softfp but no FP. Use the soft-float libraries. +MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv7e-m armv8-m\.base armv8-m\.main, \ + mthumb/march.$(ARCH)/mfloat-abi.soft=mthumb/march.$(ARCH)/mfloat-abi.softfp) -# We map all requests for ARMv7-R or ARMv7-A in ARM mode to Thumb mode and -# any FPU to VFPv3-d16 if possible. -MULTILIB_REUSE += mthumb/march.armv7=march.armv7 -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.fpv5-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.hard diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp index bef5be8..8e9226a 100644 --- a/gcc/testsuite/gcc.target/arm/multilib.exp +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -376,6 +376,310 @@ if {[multilib_config "aprofile"] } { check_multi_dir $opts $dir } } +if {[multilib_config "rmprofile"] } { + foreach {opts dir} { + {-mcpu=cortex-m0 -mfpu=auto -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=auto -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=auto -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m0 -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=auto -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-mcpu=cortex-m23 -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-mcpu=cortex-m23 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv6-m -mfpu=auto -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=auto -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m+fp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv7e-m+fp.dp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv6-m -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=auto -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.base -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv7e-m+fp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + } { + check_multi_dir $opts $dir + } +} gcc_parallel_test_enable 1