diff mbox series

[v4,03/10] elf.h: Add RISC-V definitions

Message ID 20181125233815.56392-4-agraf@suse.de
State Superseded
Headers show
Series Add RISC-V support | expand

Commit Message

Alexander Graf Nov. 25, 2018, 11:38 p.m. UTC
The RISC-V ABI document outlines ELF header structure and relocation
information. Pull the respective magic numbers into our elf header
so we can make use of them.

Signed-off-by: Alexander Graf <agraf@suse.de>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Tested-by: Bin Meng <bmeng.cn@gmail.com>

---
 include/grub/elf.h | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

-- 
2.12.3


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Comments

Daniel Kiper Jan. 17, 2019, 11:40 a.m. UTC | #1
On Mon, Nov 26, 2018 at 12:38:08AM +0100, Alexander Graf wrote:
> The RISC-V ABI document outlines ELF header structure and relocation

> information. Pull the respective magic numbers into our elf header

> so we can make use of them.

>

> Signed-off-by: Alexander Graf <agraf@suse.de>

> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

> Tested-by: Bin Meng <bmeng.cn@gmail.com>


One nit pick below. If you fix it you can add
  Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com>


> ---

>  include/grub/elf.h | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++

>  1 file changed, 59 insertions(+)

>

> diff --git a/include/grub/elf.h b/include/grub/elf.h

> index c8492f9dc..76c6a5a02 100644

> --- a/include/grub/elf.h

> +++ b/include/grub/elf.h

> @@ -247,6 +247,7 @@ typedef struct

>  #define EM_XTENSA	94		/* Tensilica Xtensa Architecture */

>  #define EM_NUM		95

>  #define EM_AARCH64	183		/* ARM 64-bit architecture */

> +#define EM_RISCV	243		/* RISC-V */

>

>  /* If it is necessary to assign new unofficial EM_* values, please

>     pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the

> @@ -2473,6 +2474,64 @@ typedef Elf32_Addr Elf32_Conflict;

>

>  #define R_X86_64_NUM		24

>

> +/* RISC-V relocations */

> +#define R_RISCV_NONE            0

> +#define R_RISCV_32              1

> +#define R_RISCV_64              2

> +#define R_RISCV_RELATIVE        3

> +#define R_RISCV_COPY            4

> +#define R_RISCV_JUMP_SLOT       5

> +#define R_RISCV_TLS_DTPMOD32    6

> +#define R_RISCV_TLS_DTPMOD64    7

> +#define R_RISCV_TLS_DTPREL32    8

> +#define R_RISCV_TLS_DTPREL64    9

> +#define R_RISCV_TLS_TPREL32     10

> +#define R_RISCV_TLS_TPREL64     11

> +

> +#define R_RISCV_BRANCH          16

> +#define R_RISCV_JAL             17

> +#define R_RISCV_CALL            18

> +#define R_RISCV_CALL_PLT        19

> +#define R_RISCV_GOT_HI20        20

> +#define R_RISCV_TLS_GOT_HI20    21

> +#define R_RISCV_TLS_GD_HI20     22

> +#define R_RISCV_PCREL_HI20      23

> +#define R_RISCV_PCREL_LO12_I    24

> +#define R_RISCV_PCREL_LO12_S    25

> +#define R_RISCV_HI20            26

> +#define R_RISCV_LO12_I          27

> +#define R_RISCV_LO12_S          28

> +#define R_RISCV_TPREL_HI20      29

> +#define R_RISCV_TPREL_LO12_I    30

> +#define R_RISCV_TPREL_LO12_S    31

> +#define R_RISCV_TPREL_ADD       32

> +#define R_RISCV_ADD8            33

> +#define R_RISCV_ADD16           34

> +#define R_RISCV_ADD32           35

> +#define R_RISCV_ADD64           36

> +#define R_RISCV_SUB8            37

> +#define R_RISCV_SUB16           38

> +#define R_RISCV_SUB32           39

> +#define R_RISCV_SUB64           40

> +#define R_RISCV_GNU_VTINHERIT   41

> +#define R_RISCV_GNU_VTENTRY     42

> +#define R_RISCV_ALIGN           43

> +#define R_RISCV_RVC_BRANCH      44

> +#define R_RISCV_RVC_JUMP        45

> +#define R_RISCV_LUI             46

> +#define R_RISCV_GPREL_I         47

> +#define R_RISCV_GPREL_S         48

> +#define R_RISCV_TPREL_I         49

> +#define R_RISCV_TPREL_S         50

> +#define R_RISCV_RELAX           51

> +#define R_RISCV_SUB6            52

> +#define R_RISCV_SET6            53

> +#define R_RISCV_SET8            54

> +#define R_RISCV_SET16           55

> +#define R_RISCV_SET32           56

> +#define R_RISCV_32_PCREL        57

> +

> +


Please drop this extra empty line.

Daniel

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diff mbox series

Patch

diff --git a/include/grub/elf.h b/include/grub/elf.h
index c8492f9dc..76c6a5a02 100644
--- a/include/grub/elf.h
+++ b/include/grub/elf.h
@@ -247,6 +247,7 @@  typedef struct
 #define EM_XTENSA	94		/* Tensilica Xtensa Architecture */
 #define EM_NUM		95
 #define EM_AARCH64	183		/* ARM 64-bit architecture */
+#define EM_RISCV	243		/* RISC-V */
 
 /* If it is necessary to assign new unofficial EM_* values, please
    pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
@@ -2473,6 +2474,64 @@  typedef Elf32_Addr Elf32_Conflict;
 
 #define R_X86_64_NUM		24
 
+/* RISC-V relocations */
+#define R_RISCV_NONE            0
+#define R_RISCV_32              1
+#define R_RISCV_64              2
+#define R_RISCV_RELATIVE        3
+#define R_RISCV_COPY            4
+#define R_RISCV_JUMP_SLOT       5
+#define R_RISCV_TLS_DTPMOD32    6
+#define R_RISCV_TLS_DTPMOD64    7
+#define R_RISCV_TLS_DTPREL32    8
+#define R_RISCV_TLS_DTPREL64    9
+#define R_RISCV_TLS_TPREL32     10
+#define R_RISCV_TLS_TPREL64     11
+
+#define R_RISCV_BRANCH          16
+#define R_RISCV_JAL             17
+#define R_RISCV_CALL            18
+#define R_RISCV_CALL_PLT        19
+#define R_RISCV_GOT_HI20        20
+#define R_RISCV_TLS_GOT_HI20    21
+#define R_RISCV_TLS_GD_HI20     22
+#define R_RISCV_PCREL_HI20      23
+#define R_RISCV_PCREL_LO12_I    24
+#define R_RISCV_PCREL_LO12_S    25
+#define R_RISCV_HI20            26
+#define R_RISCV_LO12_I          27
+#define R_RISCV_LO12_S          28
+#define R_RISCV_TPREL_HI20      29
+#define R_RISCV_TPREL_LO12_I    30
+#define R_RISCV_TPREL_LO12_S    31
+#define R_RISCV_TPREL_ADD       32
+#define R_RISCV_ADD8            33
+#define R_RISCV_ADD16           34
+#define R_RISCV_ADD32           35
+#define R_RISCV_ADD64           36
+#define R_RISCV_SUB8            37
+#define R_RISCV_SUB16           38
+#define R_RISCV_SUB32           39
+#define R_RISCV_SUB64           40
+#define R_RISCV_GNU_VTINHERIT   41
+#define R_RISCV_GNU_VTENTRY     42
+#define R_RISCV_ALIGN           43
+#define R_RISCV_RVC_BRANCH      44
+#define R_RISCV_RVC_JUMP        45
+#define R_RISCV_LUI             46
+#define R_RISCV_GPREL_I         47
+#define R_RISCV_GPREL_S         48
+#define R_RISCV_TPREL_I         49
+#define R_RISCV_TPREL_S         50
+#define R_RISCV_RELAX           51
+#define R_RISCV_SUB6            52
+#define R_RISCV_SET6            53
+#define R_RISCV_SET8            54
+#define R_RISCV_SET16           55
+#define R_RISCV_SET32           56
+#define R_RISCV_32_PCREL        57
+
+
 #ifdef GRUB_TARGET_WORDSIZE
 #if GRUB_TARGET_WORDSIZE == 32