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[209.132.180.131]) by mx.google.com with ESMTPS id b69si10547173pfe.254.2018.03.05.10.18.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 10:18:02 -0800 (PST) Received-SPF: pass (google.com: domain of libc-alpha-return-90814-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=LFWXKn6i; spf=pass (google.com: domain of libc-alpha-return-90814-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-90814-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; q=dns; s= default; b=rBh28App6dxoAndjdb3dJ666u50FCNstH1Z6hAp3BZA8/ZU26Nbyl fziiyAdrSJBJYdTPh9fsMjZjLc/fStQMKLx1sDEBj1iycNXR4LKM6p8ezmC/jjwe iehGf5b8zBntX4IHE4EWY5xRpyFqAEkL690Q4xUg68OIk4/x2VFQ/A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; s=default; bh=WcBrF4Db3x/oDKej0LcjYILq1QE=; b=LFWXKn6ibWXXDiXFhy5YrzPEWSfS 2LjkuU285uVIsG3nYY/bBLJ1ECNboCjmoMqq+sl4zp6OQtCkQLt21fI2uZvCD19r ldP3baTaLBAN4uRCQnd93u41LSOyA7aXVGIZpTxsIe8BpHhnQL5oWq4q3CLE9qXO sCzV+/PxWT6OWzQ= Received: (qmail 74354 invoked by alias); 5 Mar 2018 18:17:53 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 74344 invoked by uid 89); 5 Mar 2018 18:17:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-vk0-f67.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=IAi26+w4vM2+DUuvstsjjfUxiguo328pzPActGskX1s=; b=U83QtvVZ9CzpywtfG5KI8lt2eRRp+CCv3IkGvc5SitmkDLCAWNE+sVYXsL3J9+cMMw bJXkm31bbVBacoVHAcIdJUZBa4ckaYOP13Pd9Ny+N0IVmESbZa+pZZRt617mnVPEWuSJ BMExoAV6oxVXv88TSRCYkyHJmN3tOj5H0nxeAVxUPLaRjzJldYR2eVcxd05sI2O/xo3F GeDDLqioHfnS3t0GPWSTq6HWTQgkv0gZYQtzI85YR7iChwtg+5w3HkbGK7KfjHtrrpmG t7Eo8CJdxjW3kRKWZaQS6Zy9PyBvDf+zGULUhK+d+TOVRREqPwq0IomRBTmcFbGBm1HU OZoA== X-Gm-Message-State: APf1xPC8COJSoNQcOJMKbhteB7DFSr40QRgqtSnK60ORrFGgYyM/v27X vLgeIoQkabDQ8jiP951vdAfyXdaqVjI= X-Received: by 10.31.134.147 with SMTP id i141mr10846080vkd.128.1520273869429; Mon, 05 Mar 2018 10:17:49 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH] powerpc: Fix TLE build for SPE (BZ #22926) Date: Mon, 5 Mar 2018 15:17:45 -0300 Message-Id: <1520273865-15009-1-git-send-email-adhemerval.zanella@linaro.org> Some SPE opcodes clashes with some recent PowerISA opcodes and until recently gas did not complain about it. However binutils recently changed it and now VLE configured gas does not support to assembler some instruction that might class with VLE (HTM for instance). It also does not help that glibc build hardware lock elision support as default (regardless of assembler support). Although runtime will not actually enables TLE on SPE hardware (since kernel will not advertise it), I see little advantage on adding HTM support on SPE built glibc. SPE uses an incompatible ABI which does not allow share the same build with default powerpc and HTM code slows down SPE without any benefict. This patch fixes it by only building HTM when SPE configuration is not used. Checked with a powerpc-linux-gnuspe build. I also did some sniff tests on a e500 hardware without any issue. [BZ #22926] * sysdeps/powerpc/powerpc32/sysdep.h (ABORT_TRANSACTION_IMPL): Define empty for __SPE__. * sysdeps/powerpc/sysdep.h (ABORT_TRANSACTION): Likewise. * sysdeps/unix/sysv/linux/powerpc/elision-lock.c (__lll_lock_elision): Do not build hardware transactional code for __SPE__. * sysdeps/unix/sysv/linux/powerpc/elision-trylock.c (__lll_trylock_elision): Likewise. * sysdeps/unix/sysv/linux/powerpc/elision-unlock.c (__lll_unlock_elision): Likewise. --- ChangeLog | 13 +++++++++++++ sysdeps/powerpc/powerpc32/sysdep.h | 2 +- sysdeps/powerpc/sysdep.h | 2 +- sysdeps/unix/sysv/linux/powerpc/elision-lock.c | 2 ++ sysdeps/unix/sysv/linux/powerpc/elision-trylock.c | 2 ++ sysdeps/unix/sysv/linux/powerpc/elision-unlock.c | 4 ++++ 6 files changed, 23 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/sysdeps/powerpc/powerpc32/sysdep.h b/sysdeps/powerpc/powerpc32/sysdep.h index 8e32a2a..5f1294e 100644 --- a/sysdeps/powerpc/powerpc32/sysdep.h +++ b/sysdeps/powerpc/powerpc32/sysdep.h @@ -90,7 +90,7 @@ GOT_LABEL: ; \ cfi_endproc; \ ASM_SIZE_DIRECTIVE(name) -#if ! IS_IN(rtld) +#if !IS_IN(rtld) && !defined(__SPE__) # define ABORT_TRANSACTION_IMPL \ cmpwi 2,0; \ beq 1f; \ diff --git a/sysdeps/powerpc/sysdep.h b/sysdeps/powerpc/sysdep.h index 03db75f..8a6d236 100644 --- a/sysdeps/powerpc/sysdep.h +++ b/sysdeps/powerpc/sysdep.h @@ -174,7 +174,7 @@ we abort transaction just before syscalls. [1] Documentation/powerpc/transactional_memory.txt [Syscalls] */ -#if !IS_IN(rtld) +#if !IS_IN(rtld) && !defined(__SPE__) # define ABORT_TRANSACTION \ ({ \ if (THREAD_GET_TM_CAPABLE ()) \ diff --git a/sysdeps/unix/sysv/linux/powerpc/elision-lock.c b/sysdeps/unix/sysv/linux/powerpc/elision-lock.c index b7093fe..98a23f0 100644 --- a/sysdeps/unix/sysv/linux/powerpc/elision-lock.c +++ b/sysdeps/unix/sysv/linux/powerpc/elision-lock.c @@ -45,6 +45,7 @@ int __lll_lock_elision (int *lock, short *adapt_count, EXTRAARG int pshared) { +#ifndef __SPE__ /* adapt_count is accessed concurrently but is just a hint. Thus, use atomic accesses but relaxed MO is sufficient. */ if (atomic_load_relaxed (adapt_count) > 0) @@ -82,5 +83,6 @@ __lll_lock_elision (int *lock, short *adapt_count, EXTRAARG int pshared) aconf.skip_lock_out_of_tbegin_retries); use_lock: +#endif return LLL_LOCK ((*lock), pshared); } diff --git a/sysdeps/unix/sysv/linux/powerpc/elision-trylock.c b/sysdeps/unix/sysv/linux/powerpc/elision-trylock.c index b74a810..fabb03b 100644 --- a/sysdeps/unix/sysv/linux/powerpc/elision-trylock.c +++ b/sysdeps/unix/sysv/linux/powerpc/elision-trylock.c @@ -30,6 +30,7 @@ int __lll_trylock_elision (int *futex, short *adapt_count) { +#ifndef __SPE__ /* Implement POSIX semantics by forbiding nesting elided trylocks. */ __libc_tabort (_ABORT_NESTED_TRYLOCK); @@ -65,5 +66,6 @@ __lll_trylock_elision (int *futex, short *adapt_count) } use_lock: +#endif return lll_trylock (*futex); } diff --git a/sysdeps/unix/sysv/linux/powerpc/elision-unlock.c b/sysdeps/unix/sysv/linux/powerpc/elision-unlock.c index dcfab19..14e0680 100644 --- a/sysdeps/unix/sysv/linux/powerpc/elision-unlock.c +++ b/sysdeps/unix/sysv/linux/powerpc/elision-unlock.c @@ -23,6 +23,7 @@ int __lll_unlock_elision (int *lock, short *adapt_count, int pshared) { +#ifndef __SPE__ /* When the lock was free we're in a transaction. */ if (*lock == 0) __libc_tend (0); @@ -39,5 +40,8 @@ __lll_unlock_elision (int *lock, short *adapt_count, int pshared) lll_unlock ((*lock), pshared); } +#else + lll_unlock ((*lock), pshared); +#endif return 0; }