From patchwork Wed May 31 14:32:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 100786 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp352999qge; Wed, 31 May 2017 07:33:59 -0700 (PDT) X-Received: by 10.101.72.135 with SMTP id n7mr2503079pgs.198.1496241239001; Wed, 31 May 2017 07:33:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496241238; cv=none; d=google.com; s=arc-20160816; b=qP/bwtAJr7q5UfShC/HWmSZyx1cd3EjC6pb4QhHBEjEWoU8MfSF4geVoMcDd2o8Z/7 quuw+dkYNwxJ+0J6Pr3Gx3Wv9fhrxaeG2xLZtaIixVGeKCecP4lvAjVrxmngLPJi9Ezf /yQrQR9fvyWk7isR+pedUHrjOzAmm0zj3zlKKF2NBOZ0h1j513EneRUaE9Nxt8QBJgeZ WL7fIB9EBWEzXMnb5VJWs8H4D8G8AHUZw/Nu1VnVvH8bm2ZThb0YnLOLvFxoG+hia4q5 jaG9i7hGlZVD1af0fnild0Vc4JpIs5AYBr3t/f5j+E+1vQZSy0IuGrgLwsthFC8cAWIH jgRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=5lfiXBZoRZkoaP5rxFUkGO+ua/7tSFpvlnLs0bQhMIk=; b=ueGRrhlGO+n3lUSvacjOQcwR8/2W89HLclmI9Q0v3wh3cQscJFyi9LHs2ljTGoG1cW ogmXe93x6SkFhsGChvXlWNg82S+tswvg1xwJqWqk6K+muRl1XVFN6DHealzgjyKTPFBB RerEEXlaU4nrIbf/M8hgk4RnymjQCiDOHD2pKclOco76UGXBHy67PecxBjXT1w9MsuHd c0P7F/PmK9L304vsShuoWoJHFasYAQaaFPNI+zg9sVoxAkJ1L0KzlyK/lb0YZlA/sd6+ VmG7bW8OgR2YlZREFKy4SnZzO0qglMH3WRj8f/ynuSO0Ong2XXYl7e+bAN+LbbgTU2mH rz4A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f64si16579419pfg.362.2017.05.31.07.33.58; Wed, 31 May 2017 07:33:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751056AbdEaOd6 (ORCPT + 8 others); Wed, 31 May 2017 10:33:58 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7296 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751037AbdEaOd5 (ORCPT ); Wed, 31 May 2017 10:33:57 -0400 Received: from 172.30.72.53 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APN18852; Wed, 31 May 2017 22:33:52 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Wed, 31 May 2017 22:33:44 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [RFCv2 0/2] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Wed, 31 May 2017 15:32:11 +0100 Message-ID: <20170531143213.82100-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.592ED451.0079, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2ead8a7f23f71d41d9ff63c3e5e51625 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On certain HiSilicon platforms (Hip06/Hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve the associated ITS base address from a device IORT node. 2. Added quirk to SMMUv3 to retrieve the HW ITS address and replace the default SW MSI reserve address based on the IORT SMMU model. This is based on the following patches: 1. https://patchwork.kernel.org/patch/9740733/ 2. https://patchwork.kernel.org/patch/9730491/ Thanks, Shameer RFC v1 ---> v2 Based on Robin's review comments, :Removed the generic erratum framework. :Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. shameer (2): acpi:iort: Add new helper function to retrieve ITS base addr from IORT node iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 drivers/acpi/arm64/iort.c | 47 +++++++++++++++++++++++++++++++++++--- drivers/iommu/arm-smmu-v3.c | 49 +++++++++++++++++++++++++++++++++++++--- drivers/irqchip/irq-gic-v3-its.c | 3 ++- include/linux/acpi_iort.h | 8 ++++++- 4 files changed, 99 insertions(+), 8 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html