[3,23/23] cxl/mem: Add debugfs output for QTG related data

Message ID	168088765758.1441063.3077950661602680130.stgit@djiang5-mobl3
State	Superseded
Headers	show Return-Path: <linux-acpi-owner@vger.kernel.org> Subject: [PATCH 3 23/23] cxl/mem: Add debugfs output for QTG related data From: Dave Jiang <dave.jiang@intel.com> To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org Cc: Dan Williams <dan.j.williams@intel.com>, dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, rafael@kernel.org, lukas@wunner.de, Jonathan.Cameron@huawei.com Date: Fri, 07 Apr 2023 10:14:17 -0700 Message-ID: <168088765758.1441063.3077950661602680130.stgit@djiang5-mobl3> In-Reply-To: <168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3> References: <168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk
Series	cxl: Add support for QTG ID retrieval for CXL subsystem \| expand [3,00/23] cxl: Add support for QTG ID retrieval for CXL subsystem [3,01/23] cxl: Export QTG ids from CFMWS to sysfs [3,02/23] cxl: Add checksum verification to CDAT from CXL [3,03/23] cxl: Add support for reading CXL switch CDAT table [3,04/23] cxl: Add common helpers for cdat parsing [3,05/23] cxl: Add callback to parse the DSMAS subtables from CDAT [3,06/23] cxl: Add callback to parse the DSLBIS subtable from CDAT [3,07/23] cxl: Add callback to parse the SSLBIS subtable from CDAT [3,08/23] cxl: Add support for _DSM Function for retrieving QTG ID [3,09/23] cxl: Add helper function to retrieve ACPI handle of CXL root device [3,10/23] cxl: Add helpers to calculate pci latency for the CXL device [3,11/23] cxl: Add helper function that calculates QoS values for switches [3,12/23] cxl: Add helper function that calculate QoS values for PCI path [3,13/23] ACPI: NUMA: Create enum for memory_target hmem_attrs indexing [3,14/23] ACPI: NUMA: Add genport target allocation to the HMAT parsing [3,15/23] ACPI: NUMA: Add setting of generic port locality attributes [3,16/23] ACPI: NUMA: Add helper function to retrieve the performance attributes [3,17/23] cxl: Add helper function to retrieve generic port QoS [3,18/23] cxl: Add latency and bandwidth calculations for the CXL path [3,19/23] cxl: Wait Memory_Info_Valid before access memory related info [3,20/23] cxl: Move identify and partition query from pci probe to port probe [3,21/23] cxl: Store QTG IDs and related info to the CXL memory device context [3,22/23] cxl: Export sysfs attributes for memory device QTG ID [3,23/23] cxl/mem: Add debugfs output for QTG related data

Message ID

168088765758.1441063.3077950661602680130.stgit@djiang5-mobl3

State

Superseded

Headers

Subject: [PATCH 3 23/23] cxl/mem: Add debugfs output for QTG related data
From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org
Cc: Dan Williams <dan.j.williams@intel.com>, dan.j.williams@intel.com,
        ira.weiny@intel.com, vishal.l.verma@intel.com,
        alison.schofield@intel.com, rafael@kernel.org, lukas@wunner.de,
        Jonathan.Cameron@huawei.com
Date: Fri, 07 Apr 2023 10:14:17 -0700
Message-ID: <168088765758.1441063.3077950661602680130.stgit@djiang5-mobl3>
In-Reply-To: <168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3>
References: <168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3>
User-Agent: StGit/1.5
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Precedence: bulk

Series

cxl: Add support for QTG ID retrieval for CXL subsystem | expand

Commit Message

Dave Jiang April 7, 2023, 5:14 p.m. UTC

Add debugfs output to /sys/kernel/debug/cxl/memX/qtgmap
The debugfs attribute will dump out all the DSMAS ranges and the associated
QTG ID exported by the CXL device CDAT.

Suggested-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
 Documentation/ABI/testing/debugfs-cxl |   11 +++++++++++
 drivers/cxl/mem.c                     |   16 ++++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 Documentation/ABI/testing/debugfs-cxl

diff --git a/Documentation/ABI/testing/debugfs-cxl b/Documentation/ABI/testing/debugfs-cxl
new file mode 100644
index 000000000000..0f36eeb7e59b
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-cxl
@@ -0,0 +1,11 @@ 
+What:		/sys/kernel/debug/cxl/memX/qtg_map
+Date:		Mar, 2023
+KernelVersion:	v6.4
+Contact:	linux-cxl@vger.kernel.org
+Description:
+		(RO) Entries of all Device Physical Address (DPA) ranges
+		provided by the device Coherent Device Attributes Table (CDAT)
+		Device Scoped Memory Affinity Structure (DSMAS) entries with
+		the matching QoS Throttling Group (QTG) id calculated from the
+		latency and bandwidth of the CXL path from the memory device
+		to the CPU.
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 39c4b54f0715..bf2cb5a54a7f 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -45,6 +45,21 @@  static int cxl_mem_dpa_show(struct seq_file *file, void *data)
 	return 0;
 }
 
+static int cxl_mem_qtg_show(struct seq_file *file, void *data)
+{
+	struct device *dev = file->private;
+	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
+	struct qos_prop_entry *qos;
+
+	list_for_each_entry(qos, &cxlmd->qos_list, list) {
+		seq_printf(file, "%08llx-%08llx : QTG ID %u\n",
+			   qos->dpa_range.start, qos->dpa_range.end,
+			   qos->qtg_id);
+	}
+
+	return 0;
+}
+
 static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
 				 struct cxl_dport *parent_dport)
 {
@@ -117,6 +132,7 @@  static int cxl_mem_probe(struct device *dev)
 
 	dentry = cxl_debugfs_create_dir(dev_name(dev));
 	debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show);
+	debugfs_create_devm_seqfile(dev, "qtgmap", dentry, cxl_mem_qtg_show);
 	rc = devm_add_action_or_reset(dev, remove_debugfs, dentry);
 	if (rc)
 		return rc;

[3,23/23] cxl/mem: Add debugfs output for QTG related data

Commit Message

Patch