From patchwork Wed Aug 24 05:04:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 3641 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 82ABF23FA2 for ; Wed, 24 Aug 2011 05:01:39 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 64B62A183D6 for ; Wed, 24 Aug 2011 05:01:39 +0000 (UTC) Received: by bkbzs2 with SMTP id zs2so992124bkb.11 for ; Tue, 23 Aug 2011 22:01:39 -0700 (PDT) Received: by 10.204.146.140 with SMTP id h12mr1852477bkv.226.1314162099051; Tue, 23 Aug 2011 22:01:39 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.41.75 with SMTP id n11cs668bke; Tue, 23 Aug 2011 22:01:38 -0700 (PDT) Received: by 10.229.2.99 with SMTP id 35mr3109522qci.280.1314162097886; Tue, 23 Aug 2011 22:01:37 -0700 (PDT) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe003.messaging.microsoft.com. [216.32.181.183]) by mx.google.com with ESMTPS id fy4si1033618qab.5.2011.08.23.22.01.37 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Aug 2011 22:01:37 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.181.183 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=216.32.181.183; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.183 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: from mail15-ch1-R.bigfish.com (216.32.181.168) by CH1EHSOBE017.bigfish.com (10.43.70.67) with Microsoft SMTP Server id 14.1.225.22; Wed, 24 Aug 2011 05:01:36 +0000 Received: from mail15-ch1 (localhost.localdomain [127.0.0.1]) by mail15-ch1-R.bigfish.com (Postfix) with ESMTP id BFF888C836D; Wed, 24 Aug 2011 05:01:36 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail15-ch1 (localhost.localdomain [127.0.0.1]) by mail15-ch1 (MessageSwitch) id 131416206893421_10582; Wed, 24 Aug 2011 05:01:08 +0000 (UTC) Received: from CH1EHSMHS016.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.240]) by mail15-ch1.bigfish.com (Postfix) with ESMTP id 280D54A808E; Wed, 24 Aug 2011 04:59:33 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS016.bigfish.com (10.43.70.16) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 24 Aug 2011 04:59:32 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Tue, 23 Aug 2011 23:59:31 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7O4xOaA004658; Tue, 23 Aug 2011 23:59:30 -0500 (CDT) From: Jason Liu To: CC: , Subject: [[PATCH v2 3/6] ARM: mx27: Print silicon revision on boot Date: Wed, 24 Aug 2011 13:04:34 +0800 Message-ID: <1314162277-2840-4-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314162277-2840-1-git-send-email-jason.hui@linaro.org> References: <1314162277-2840-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Silicon revision is useful information to have during kernel boot. Print the MX27 silicon revision. Signed-off-by: Fabio Estevam Signed-off-by: Jason Liu Cc: Sascha Hauer --- Resend: The patch based on Fabio initial patch, I did some change to use generic function for displaying silicon revision and also some naming change to avoid using the generic name --- arch/arm/mach-imx/clock-imx27.c | 2 ++ arch/arm/mach-imx/cpu-imx27.c | 28 +++++++++++++--------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 6912b82..e6b1beb 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -751,6 +751,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&gpio_clk); clk_enable(&emi_clk); clk_enable(&iim_clk); + imx_print_silicon_rev("i.MX27", mx27_revision()); + clk_disable(&iim_clk); #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) clk_enable(&uart1_clk); diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index 3b117be..ff38e15 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -26,12 +26,12 @@ #include -static int cpu_silicon_rev = -1; -static int cpu_partnumber; +static int mx27_cpu_rev = -1; +static int mx27_cpu_partnumber; #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ -static void query_silicon_parameter(void) +static int mx27_read_cpu_rev(void) { u32 val; /* @@ -42,20 +42,18 @@ static void query_silicon_parameter(void) val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); + mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); + switch (val >> 28) { case 0: - cpu_silicon_rev = IMX_CHIP_REVISION_1_0; - break; + return IMX_CHIP_REVISION_1_0; case 1: - cpu_silicon_rev = IMX_CHIP_REVISION_2_0; - break; + return IMX_CHIP_REVISION_2_0; case 2: - cpu_silicon_rev = IMX_CHIP_REVISION_2_1; - break; + return IMX_CHIP_REVISION_2_1; default: - cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN; + return IMX_CHIP_REVISION_UNKNOWN; } - cpu_partnumber = (int)((val >> 12) & 0xFFFF); } /* @@ -65,12 +63,12 @@ static void query_silicon_parameter(void) */ int mx27_revision(void) { - if (cpu_silicon_rev == -1) - query_silicon_parameter(); + if (mx27_cpu_rev == -1) + mx27_cpu_rev = mx27_read_cpu_rev(); - if (cpu_partnumber != 0x8821) + if (mx27_cpu_partnumber != 0x8821) return -EINVAL; - return cpu_silicon_rev; + return mx27_cpu_rev; } EXPORT_SYMBOL(mx27_revision);