From patchwork Wed Nov 23 11:12:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5291 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C999E23E07 for ; Wed, 23 Nov 2011 11:13:29 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7C916A1866C for ; Wed, 23 Nov 2011 11:13:29 +0000 (UTC) Received: by yenl7 with SMTP id l7so370431yen.11 for ; Wed, 23 Nov 2011 03:13:29 -0800 (PST) Received: by 10.152.105.226 with SMTP id gp2mr14094197lab.28.1322046808426; Wed, 23 Nov 2011 03:13:28 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs225897lal; Wed, 23 Nov 2011 03:13:28 -0800 (PST) Received: by 10.180.85.67 with SMTP id f3mr17967971wiz.52.1322046806529; Wed, 23 Nov 2011 03:13:26 -0800 (PST) Received: from DB3EHSOBE002.bigfish.com (db3ehsobe002.messaging.microsoft.com. [213.199.154.140]) by mx.google.com with ESMTPS id m20si8210070wbh.109.2011.11.23.03.13.26 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 23 Nov 2011 03:13:26 -0800 (PST) Received-SPF: neutral (google.com: 213.199.154.140 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=213.199.154.140; Authentication-Results: mx.google.com; spf=neutral (google.com: 213.199.154.140 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail78-db3-R.bigfish.com (10.3.81.245) by DB3EHSOBE002.bigfish.com (10.3.84.22) with Microsoft SMTP Server id 14.1.225.22; Wed, 23 Nov 2011 11:12:44 +0000 Received: from mail78-db3 (localhost [127.0.0.1]) by mail78-db3-R.bigfish.com (Postfix) with ESMTP id 077C56A0328; Wed, 23 Nov 2011 11:13:46 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail78-db3 (localhost.localdomain [127.0.0.1]) by mail78-db3 (MessageSwitch) id 1322046825772921_13636; Wed, 23 Nov 2011 11:13:45 +0000 (UTC) Received: from DB3EHSMHS007.bigfish.com (unknown [10.3.81.251]) by mail78-db3.bigfish.com (Postfix) with ESMTP id B5A71540042; Wed, 23 Nov 2011 11:13:45 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS007.bigfish.com (10.3.87.107) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 23 Nov 2011 11:12:44 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.339.2; Wed, 23 Nov 2011 05:13:23 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pANBDAMi008802; Wed, 23 Nov 2011 05:13:20 -0600 (CST) From: Richard Zhao To: CC: , , , , , , , Sascha Hauer Subject: [RFC V1 3/8] clk: Add support for simple dividers Date: Wed, 23 Nov 2011 19:12:30 +0800 Message-ID: <1322046755-13511-4-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1322046755-13511-1-git-send-email-richard.zhao@linaro.org> References: <1322046755-13511-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com This patch adds support for the most common type of divider, which expects a register, width and shift values to desacribe the location of the divider. The divider can be zero based or one based (div = reg_val + 1 vs. div = reg_val). Signed-off-by: Sascha Hauer Signed-off-by: Richard Zhao --- drivers/clk/Kconfig | 4 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-divider.c | 132 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk.h | 34 ++++++++++++ 4 files changed, 171 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/clk-divider.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 8f8e7ac..979d4df 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,10 @@ config GENERIC_CLK_BASIC Allow use of basic, single-function clock types. These common definitions can be used across many platforms. +config GENERIC_CLK_DIVIDER + bool + depends on GENERIC_CLK + config GENERIC_CLK_SYSFS bool "Clock tree topology and debug info" depends on EXPERIMENTAL && GENERIC_CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 806a9999..894ff3f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o obj-$(CONFIG_GENERIC_CLK) += clk.o obj-$(CONFIG_GENERIC_CLK_BASIC) += clk-basic.o +obj-$(CONFIG_GENERIC_CLK_DIVIDER) += clk-divider.o obj-$(CONFIG_GENERIC_CLK_SYSFS) += clk-sysfs.o diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c new file mode 100644 index 0000000..7af9f6f --- /dev/null +++ b/drivers/clk/clk-divider.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2011 Sascha Hauer, Pengutronix + * Copyright (C) 2011 Richard Zhao, Linaro + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Standard functionality for the common clock API. + */ +#include +#include +#include + +#define to_clk_divider(ck) container_of(ck, struct clk_divider, clk) + +static unsigned long clk_divider_recalc_rate(struct clk *clk) +{ + struct clk_divider *divider = to_clk_divider(clk); + unsigned long rate = clk->parent->rate; + unsigned int div; + + div = readl(divider->reg) >> divider->shift; + div &= (1 << divider->width) - 1; + + if (!(divider->flags & CLK_DIVIDER_FLAG_ONE_BASED)) + div++; + + return rate / div; +} + +#define account_for_rounding_errors 1 + +static int clk_divider_bestdiv(struct clk *clk, unsigned long rate, + unsigned long *best_parent_rate) +{ + struct clk_divider *divider = to_clk_divider(clk); + int i, bestdiv = 0; + unsigned long parent_rate, best = 0, now, maxdiv; + + maxdiv = (1 << divider->width); + + if (divider->flags & CLK_DIVIDER_FLAG_ONE_BASED) + maxdiv--; + + if (!(clk->flags & CLK_PARENT_SET_RATE)) { + parent_rate = clk->parent->rate; + bestdiv = parent_rate / rate; + bestdiv = bestdiv == 0 ? 1 : bestdiv; + bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; + goto out; + } + + /* + * The maximum divider we can use without overflowing + * unsigned long in rate * i below + */ + maxdiv = min(ULONG_MAX / rate, maxdiv); + + for (i = 1; i <= maxdiv; i++) { + parent_rate = clk_round_rate(clk->parent, + (rate + account_for_rounding_errors) * i); + now = parent_rate / i; + + if (now <= rate && now >= best) { + bestdiv = i; + best = now; + } + } + + if (!bestdiv) { + bestdiv = (1 << divider->width); + parent_rate = clk_round_rate(clk->parent, 1); + } else { + parent_rate = best * bestdiv; + } + +out: + if (best_parent_rate) + *best_parent_rate = parent_rate; + + return bestdiv; +} + +static long clk_divider_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + unsigned long best_parent_rate; + int div = clk_divider_bestdiv(clk, rate, &best_parent_rate); + if (prate) { + if (best_parent_rate == clk->parent->rate) + *prate = 0; + else + *prate = best_parent_rate; + } + + return best_parent_rate / div; +} + +static int clk_divider_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long best_parent_rate; + struct clk_divider *divider = to_clk_divider(clk); + unsigned int div; + unsigned long flags = 0; + u32 val; + + div = clk_divider_bestdiv(clk, rate, &best_parent_rate); + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + + if (!(divider->flags & CLK_DIVIDER_FLAG_ONE_BASED)) + div--; + + val = readl(divider->reg); + val &= ~(((1 << divider->width) - 1) << divider->shift); + val |= div << divider->shift; + writel(val, divider->reg); + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + + return 0; +} + +struct clk_hw_ops clk_divider_ops = { + .recalc_rate = clk_divider_recalc_rate, + .round_rate = clk_divider_round_rate, + .set_rate = clk_divider_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_ops); diff --git a/include/linux/clk.h b/include/linux/clk.h index 99337ca..1a6c81c 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -168,6 +168,40 @@ int clk_register_gate(struct device *dev, const char *name, unsigned long flags, #endif +#ifdef CONFIG_GENERIC_CLK_DIVIDER + +#include + +/** + * clock divider + * + * @clk clock source + * @reg register containing the divider + * @shift shift to the divider + * @width width of the divider + * @lock register lock + * + * This clock implements get_rate/set_rate/round_rate. + * + * The divider is calculated as div = reg_val + 1 + * or if CLK_DIVIDER_FLAG_ONE_BASED is set as div = reg_val + * (with reg_val == 0 considered invalid) + */ +struct clk_divider { + struct clk clk; + void __iomem *reg; + unsigned char shift; + unsigned char width; + spinlock_t *lock; +#define CLK_DIVIDER_FLAG_ONE_BASED (1 << 0) + unsigned int flags; + struct clk_hw *parent; +}; + +extern struct clk_hw_ops clk_divider_ops; + +#endif /* CONFIG_GENERIC_CLK_DIVIDER */ + /** * clk_init - initialize the data structures in a struct clk * @dev: device initializing this clk, placeholder for now