From patchwork Thu Dec 8 01:28:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5535 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3B3B723E0C for ; Thu, 8 Dec 2011 01:28:59 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 2A134A18784 for ; Thu, 8 Dec 2011 01:28:59 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 17so1574286bke.11 for ; Wed, 07 Dec 2011 17:28:59 -0800 (PST) Received: by 10.204.156.141 with SMTP id x13mr492775bkw.54.1323307738942; Wed, 07 Dec 2011 17:28:58 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs84025bkc; Wed, 7 Dec 2011 17:28:58 -0800 (PST) Received: by 10.229.231.12 with SMTP id jo12mr117750qcb.258.1323307736728; Wed, 07 Dec 2011 17:28:56 -0800 (PST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com. [216.32.181.181]) by mx.google.com with ESMTPS id y14si1173319qct.54.2011.12.07.17.28.56 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Dec 2011 17:28:56 -0800 (PST) Received-SPF: neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=216.32.181.181; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail60-ch1-R.bigfish.com (10.43.68.247) by CH1EHSOBE003.bigfish.com (10.43.70.53) with Microsoft SMTP Server id 14.1.225.23; Thu, 8 Dec 2011 01:28:55 +0000 Received: from mail60-ch1 (localhost [127.0.0.1]) by mail60-ch1-R.bigfish.com (Postfix) with ESMTP id 40B4D44030D; Thu, 8 Dec 2011 01:28:56 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail60-ch1 (localhost.localdomain [127.0.0.1]) by mail60-ch1 (MessageSwitch) id 1323307733944784_20364; Thu, 8 Dec 2011 01:28:53 +0000 (UTC) Received: from CH1EHSMHS014.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.244]) by mail60-ch1.bigfish.com (Postfix) with ESMTP id E0ADE540051; Thu, 8 Dec 2011 01:28:53 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS014.bigfish.com (10.43.70.14) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 8 Dec 2011 01:28:50 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.339.2; Wed, 7 Dec 2011 19:28:50 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pB81SiGq025900; Wed, 7 Dec 2011 19:28:48 -0600 (CST) From: Richard Zhao To: CC: , , , Subject: [PATCH V2 1/2] ARM: mx51/53: correct misuse of _clk_max_enable and _clk_max_disable Date: Thu, 8 Dec 2011 09:28:33 +0800 Message-ID: <1323307714-21290-2-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323307714-21290-1-git-send-email-richard.zhao@linaro.org> References: <1323307714-21290-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com _clk_max_enable and _clk_max_disable should only be used by ahb_max_clk, rather not unrelated clocks. Signed-off-by: Richard Zhao --- arch/arm/mach-imx/clock-mx51-mx53.c | 40 +++++++++++++++++----------------- 1 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-imx/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c index 0847050..716533b 100644 --- a/arch/arm/mach-imx/clock-mx51-mx53.c +++ b/arch/arm/mach-imx/clock-mx51-mx53.c @@ -1013,7 +1013,7 @@ static struct clk mipi_hsp_clk = { .secondary = s, \ } -#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \ +#define DEFINE_CLOCK_ESDHC(name, i, er, es, pfx, p, s) \ static struct clk name = { \ .id = i, \ .enable_reg = er, \ @@ -1021,8 +1021,8 @@ static struct clk mipi_hsp_clk = { .get_rate = pfx##_get_rate, \ .set_rate = pfx##_set_rate, \ .set_parent = pfx##_set_parent, \ - .enable = _clk_max_enable, \ - .disable = _clk_max_disable, \ + .enable = _clk_ccgr_enable, \ + .disable = _clk_ccgr_disable, \ .parent = p, \ .secondary = s, \ } @@ -1341,18 +1341,18 @@ DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, /* eSDHC */ DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); -DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); +DEFINE_CLOCK_ESDHC(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); /* mx51 specific */ -DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, +DEFINE_CLOCK_ESDHC(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); static struct clk esdhc3_clk = { @@ -1361,8 +1361,8 @@ static struct clk esdhc3_clk = { .set_parent = clk_esdhc3_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc3_ipg_clk, }; static struct clk esdhc4_clk = { @@ -1371,8 +1371,8 @@ static struct clk esdhc4_clk = { .set_parent = clk_esdhc4_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc4_ipg_clk, }; @@ -1383,12 +1383,12 @@ static struct clk esdhc2_mx53_clk = { .set_parent = clk_esdhc2_mx53_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc3_ipg_clk, }; -DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, +DEFINE_CLOCK_ESDHC(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk); static struct clk esdhc4_mx53_clk = { @@ -1397,17 +1397,17 @@ static struct clk esdhc4_mx53_clk = { .set_parent = clk_esdhc4_mx53_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc4_ipg_clk, }; static struct clk sata_clk = { .parent = &ipg_clk, - .enable = _clk_max_enable, + .enable = _clk_ccgr_enable, .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, - .disable = _clk_max_disable, + .disable = _clk_ccgr_disable, }; static struct clk ahci_phy_clk = {