From patchwork Mon Dec 12 03:42:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5585 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B120023E03 for ; Mon, 12 Dec 2011 03:43:04 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 9FDAAA1853E for ; Mon, 12 Dec 2011 03:43:04 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 17so6647003bke.11 for ; Sun, 11 Dec 2011 19:43:04 -0800 (PST) Received: by 10.204.133.213 with SMTP id g21mr5231014bkt.126.1323661384215; Sun, 11 Dec 2011 19:43:04 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs36497bkc; Sun, 11 Dec 2011 19:43:04 -0800 (PST) Received: by 10.68.199.168 with SMTP id jl8mr2376521pbc.25.1323661381966; Sun, 11 Dec 2011 19:43:01 -0800 (PST) Received: from VA3EHSOBE004.bigfish.com (va3ehsobe004.messaging.microsoft.com. [216.32.180.14]) by mx.google.com with ESMTPS id m3si21751592pbs.70.2011.12.11.19.43.01 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 11 Dec 2011 19:43:01 -0800 (PST) Received-SPF: neutral (google.com: 216.32.180.14 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=216.32.180.14; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.14 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail78-va3-R.bigfish.com (10.7.14.250) by VA3EHSOBE004.bigfish.com (10.7.40.24) with Microsoft SMTP Server id 14.1.225.23; Mon, 12 Dec 2011 03:42:58 +0000 Received: from mail78-va3 (localhost [127.0.0.1]) by mail78-va3-R.bigfish.com (Postfix) with ESMTP id C78C6601B4; Mon, 12 Dec 2011 03:42:58 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail78-va3 (localhost.localdomain [127.0.0.1]) by mail78-va3 (MessageSwitch) id 1323661378443995_22146; Mon, 12 Dec 2011 03:42:58 +0000 (UTC) Received: from VA3EHSMHS014.bigfish.com (unknown [10.7.14.243]) by mail78-va3.bigfish.com (Postfix) with ESMTP id 6298A401FB; Mon, 12 Dec 2011 03:42:58 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS014.bigfish.com (10.7.99.24) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 12 Dec 2011 03:42:58 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.355.3; Sun, 11 Dec 2011 21:42:58 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pBC3geqI019860; Sun, 11 Dec 2011 21:42:56 -0600 (CST) From: Richard Zhao To: CC: , , , , , Richard Zhao Subject: [PATCH 6/7] arm/imx6q: add cpufreq support Date: Mon, 12 Dec 2011 11:42:31 +0800 Message-ID: <1323661352-10291-7-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323661352-10291-1-git-send-email-richard.zhao@linaro.org> References: <1323661352-10291-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Signed-off-by: Richard Zhao --- arch/arm/mach-imx/Kconfig | 1 + arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/cpu_op-imx6q.c | 78 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index fbd414b..7d813a3 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -837,6 +837,7 @@ config SOC_IMX6Q select ARM_GIC select CACHE_L2X0 select CPU_V7 + select ARCH_HAS_CPUFREQ select HAVE_ARM_SCU select HAVE_IMX_GPC select HAVE_IMX_MMDC diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 9cf630a..2dfe4a7 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -72,7 +72,7 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o +obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o cpu_op-imx6q.o # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o diff --git a/arch/arm/mach-imx/cpu_op-imx6q.c b/arch/arm/mach-imx/cpu_op-imx6q.c new file mode 100644 index 0000000..8807b96 --- /dev/null +++ b/arch/arm/mach-imx/cpu_op-imx6q.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +static u32 arm_max_freq; +static int num_cpu_op; + +/* working point(wp): 0 - 1GHzMHz; 1 - 800MHz, 3 - 400MHz, 4 - 160MHz */ +static struct cpu_op mx6q_cpu_op_1G[] = { + { + .cpu_rate = 996000000, + .cpu_voltage = 1225000,}, + { + .cpu_rate = 792000000, + .cpu_voltage = 1100000,}, + { + .cpu_rate = 396000000, + .cpu_voltage = 950000,}, + { + .cpu_rate = 198000000, + .cpu_voltage = 850000,}, +}; + +static struct cpu_op mx6q_cpu_op[] = { + { + .cpu_rate = 792000000, + .cpu_voltage = 1100000,}, + { + .cpu_rate = 396000000, + .cpu_voltage = 950000,}, + { + .cpu_rate = 198000000, + .cpu_voltage = 850000,}, +}; + +struct cpu_op *mx6q_get_cpu_op(int *op) +{ + if (arm_max_freq == 1000) { + *op = num_cpu_op = ARRAY_SIZE(mx6q_cpu_op_1G); + return mx6q_cpu_op_1G; + } else { + *op = num_cpu_op = ARRAY_SIZE(mx6q_cpu_op); + return mx6q_cpu_op; + } +} + +static int __init mx6q_cpu_op_init(void) +{ + get_cpu_op = mx6q_get_cpu_op; + return 0; +} + +core_initcall(mx6q_cpu_op_init); + +static int __init set_arm_max_freq(char *p) +{ + if (strncmp(p, "1000", 4) == 0) + arm_max_freq = 1000; + else if (strncmp(p, "800", 3) == 0) + arm_max_freq = 800; + return 0; +} + +early_param("arm_freq", set_arm_max_freq);