From patchwork Thu Jan 5 05:20:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Chen X-Patchwork-Id: 6060 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9433923E16 for ; Thu, 5 Jan 2012 05:20:47 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7F8E3A18269 for ; Thu, 5 Jan 2012 05:20:47 +0000 (UTC) Received: by eaac11 with SMTP id c11so141982eaa.11 for ; Wed, 04 Jan 2012 21:20:47 -0800 (PST) Received: by 10.205.132.148 with SMTP id hu20mr201844bkc.96.1325740847260; Wed, 04 Jan 2012 21:20:47 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs391965bkc; Wed, 4 Jan 2012 21:20:47 -0800 (PST) Received: by 10.180.93.193 with SMTP id cw1mr1124448wib.5.1325740845617; Wed, 04 Jan 2012 21:20:45 -0800 (PST) Received: from TX2EHSOBE007.bigfish.com (tx2ehsobe004.messaging.microsoft.com. [65.55.88.14]) by mx.google.com with ESMTPS id e7si23430799wed.37.2012.01.04.21.20.44 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Jan 2012 21:20:45 -0800 (PST) Received-SPF: neutral (google.com: 65.55.88.14 is neither permitted nor denied by best guess record for domain of jason.chen@linaro.org) client-ip=65.55.88.14; Authentication-Results: mx.google.com; spf=neutral (google.com: 65.55.88.14 is neither permitted nor denied by best guess record for domain of jason.chen@linaro.org) smtp.mail=jason.chen@linaro.org Received: from mail18-tx2-R.bigfish.com (10.9.14.243) by TX2EHSOBE007.bigfish.com (10.9.40.27) with Microsoft SMTP Server id 14.1.225.23; Thu, 5 Jan 2012 05:20:43 +0000 Received: from mail18-tx2 (localhost [127.0.0.1]) by mail18-tx2-R.bigfish.com (Postfix) with ESMTP id B0F956603B4; Thu, 5 Jan 2012 05:20:43 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zcb8kzzz1202hzz8275bh8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail18-tx2 (localhost.localdomain [127.0.0.1]) by mail18-tx2 (MessageSwitch) id 1325740843204307_15056; Thu, 5 Jan 2012 05:20:43 +0000 (UTC) Received: from TX2EHSMHS034.bigfish.com (unknown [10.9.14.248]) by mail18-tx2.bigfish.com (Postfix) with ESMTP id 2AEE720052; Thu, 5 Jan 2012 05:20:43 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS034.bigfish.com (10.9.99.134) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 5 Jan 2012 05:20:43 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.355.3; Wed, 4 Jan 2012 23:20:42 -0600 Received: from weitway.ap.freescale.net ([10.192.242.173]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id q055Ke16016707; Wed, 4 Jan 2012 23:20:40 -0600 (CST) From: Jason Chen To: CC: , , Subject: [PATCH] arm: imx6q: bypass anatop regulator during suspend Date: Thu, 5 Jan 2012 13:20:42 +0800 Message-ID: <1325740842-5464-1-git-send-email-jason.chen@linaro.org> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com enable bit CCM_CLPCR_wb_per_at_lpm to decrease leakage during suspend. enable bit CCM_CCR_RBC_EN to disable/bypass anatop regulator during suspend. Signed-off-by: Jason Chen Signed-off-by: Jason Chen --- arch/arm/mach-imx/clock-imx6q.c | 31 +++++++++++++++--------- arch/arm/mach-imx/pm-imx6q.c | 48 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index 56a7a3f..11d2453 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -115,6 +115,8 @@ #define CG14 28 #define CG15 30 +#define BM_CCR_RBC_EN (0x1 << 27) + #define BM_CCSR_PLL1_SW_SEL (0x1 << 2) #define BM_CCSR_STEP_SEL (0x1 << 8) @@ -1916,33 +1918,38 @@ static struct clk_lookup lookups[] = { int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { - u32 val = readl_relaxed(CLPCR); + u32 clpcr = readl_relaxed(CLPCR); + u32 ccr = readl_relaxed(CCR); - val &= ~BM_CLPCR_LPM; + clpcr &= ~(BM_CLPCR_LPM | BM_CLPCR_VSTBY | BM_CLPCR_SBYOS + | BM_CLPCR_STBY_COUNT | BM_CLPCR_WB_PER_AT_LPM); + ccr &= ~(BM_CCR_RBC_EN); switch (mode) { case WAIT_CLOCKED: break; case WAIT_UNCLOCKED: - val |= 0x1 << BP_CLPCR_LPM; + clpcr |= 0x1 << BP_CLPCR_LPM; break; case STOP_POWER_ON: - val |= 0x2 << BP_CLPCR_LPM; + clpcr |= 0x2 << BP_CLPCR_LPM; break; case WAIT_UNCLOCKED_POWER_OFF: - val |= 0x1 << BP_CLPCR_LPM; - val &= ~BM_CLPCR_VSTBY; - val &= ~BM_CLPCR_SBYOS; + clpcr |= 0x1 << BP_CLPCR_LPM; break; case STOP_POWER_OFF: - val |= 0x2 << BP_CLPCR_LPM; - val |= 0x3 << BP_CLPCR_STBY_COUNT; - val |= BM_CLPCR_VSTBY; - val |= BM_CLPCR_SBYOS; + clpcr |= 0x2 << BP_CLPCR_LPM; + clpcr |= 0x3 << BP_CLPCR_STBY_COUNT; + clpcr |= BM_CLPCR_VSTBY; + clpcr |= BM_CLPCR_SBYOS; + clpcr |= BM_CLPCR_WB_PER_AT_LPM; + /* assert anatop_reg_bypass signal */ + ccr |= BM_CCR_RBC_EN; break; default: return -EINVAL; } - writel_relaxed(val, CLPCR); + writel_relaxed(clpcr, CLPCR); + writel_relaxed(ccr, CCR); return 0; } diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index f20f191..72a1399 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,41 @@ #include extern unsigned long phys_l2x0_saved_regs; +static void __iomem *anatop_base; + +#define ANATOP_REG_2P5 0x130 +#define BM_ANATOP_REG_2P5_WEAK_EN (0x1 << 18) + +static int imx6q_anatop_reg_pre_suspend(void) +{ + /* + * enable anatop weak 2p5 regulator, which should use + * regulator API after anatop regulator implementation. + */ + if (anatop_base) { + unsigned int reg_2p5; + reg_2p5 = readl(anatop_base + ANATOP_REG_2P5); + reg_2p5 |= BM_ANATOP_REG_2P5_WEAK_EN; + writel(reg_2p5, anatop_base + ANATOP_REG_2P5); + } else + return -EINVAL; + + return 0; +} + +static void imx6q_anatop_reg_post_resume(void) +{ + /* + * disable anatop weak 2p5 regulator, which should use + * regulator API after anatop regulator implementation. + */ + if (anatop_base) { + unsigned int reg_2p5; + reg_2p5 = readl(anatop_base + ANATOP_REG_2P5); + reg_2p5 &= ~BM_ANATOP_REG_2P5_WEAK_EN; + writel(reg_2p5, anatop_base + ANATOP_REG_2P5); + } +} static int imx6q_suspend_finish(unsigned long val) { @@ -33,6 +69,8 @@ static int imx6q_pm_enter(suspend_state_t state) { switch (state) { case PM_SUSPEND_MEM: + if (imx6q_anatop_reg_pre_suspend() < 0) + return -EINVAL; imx6q_set_lpm(STOP_POWER_OFF); imx_gpc_pre_suspend(); imx_set_cpu_jump(0, v7_cpu_resume); @@ -40,6 +78,7 @@ static int imx6q_pm_enter(suspend_state_t state) cpu_suspend(0, imx6q_suspend_finish); imx_smp_prepare(); imx_gpc_post_resume(); + imx6q_anatop_reg_post_resume(); break; default: return -EINVAL; @@ -55,6 +94,15 @@ static const struct platform_suspend_ops imx6q_pm_ops = { void __init imx6q_pm_init(void) { + struct device_node *np; + + /* + * remap anatop to adjust anatop regulator, which should + * remove after anatop regulator driver implementation. + */ + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); + anatop_base = of_iomap(np, 0); + /* * The l2x0 core code provides an infrastucture to save and restore * l2x0 registers across suspend/resume cycle. But because imx6q