From patchwork Wed Mar 14 13:05:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 7290 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 79D3323DEE for ; Wed, 14 Mar 2012 13:05:27 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 411D2A18743 for ; Wed, 14 Mar 2012 13:05:27 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so3119093iag.11 for ; Wed, 14 Mar 2012 06:05:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=3nn/GNcHkXXLpz6tlxvx3mNNBenyPtypOVmS1rCksvQ=; b=GoU9NO4+bImKSlC+mB79J+T67KX+ZoUsPernjiZnXkdVOyLPODBJVSJVnzmG+R1ibL Vsq3EKGL9lANgX9wLAOGWY71QjCIxWyhW2eOMxn3JCxFIqPYr6HfdpkuYg9xlCXJGhSB GtEQ0vnQrLhZeH+lIkB7qgO6kRn13mt38Pum7+5TW5Tq/ekTqgg3AqLawPOCOskNFeJK mw0PSP/6CtkwAp3vJmhGq6mX3vy+dvWqTC+Qz1gmqYc9yEFPjLs568RIrLM0Rl7EH8Ip 76jH27mZXh6URyZlZ4d9v5OWH4dDbFQHh9UuuHt/WSwKEcwxgdimLYOC7BziXqDCUS4O 22OQ== Received: by 10.42.145.72 with SMTP id e8mr3649226icv.0.1331730326948; Wed, 14 Mar 2012 06:05:26 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp9549ibg; Wed, 14 Mar 2012 06:05:26 -0700 (PDT) Received: by 10.180.85.165 with SMTP id i5mr6194365wiz.11.1331730325712; Wed, 14 Mar 2012 06:05:25 -0700 (PDT) Received: from mail-we0-f178.google.com (mail-we0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id v6si4831623weq.146.2012.03.14.06.05.25 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Mar 2012 06:05:25 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) smtp.mail=lee.jones@linaro.org Received: by mail-we0-f178.google.com with SMTP id a13so2184022wer.37 for ; Wed, 14 Mar 2012 06:05:25 -0700 (PDT) Received: by 10.216.135.97 with SMTP id t75mr1529529wei.60.1331730325134; Wed, 14 Mar 2012 06:05:25 -0700 (PDT) Received: from localhost.localdomain (cpc1-aztw13-0-0-cust473.18-1.cable.virginmedia.com. [77.102.241.218]) by mx.google.com with ESMTPS id fi4sm11477024wib.4.2012.03.14.06.05.23 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Mar 2012 06:05:24 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org Cc: linus.walleij@linaro.org, arnd@arndb.de, niklas.hernaeus@stericsson.com, Lee Jones Subject: [PATCH 09/10] ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree Date: Wed, 14 Mar 2012 13:05:05 +0000 Message-Id: <1331730306-11461-10-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org> References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org> X-Gm-Message-State: ALoCoQkoy0y7o9yeV0v3ejBnIwTrN1I8xBCTP9LMyLFRnisjsX7O049ra37ncq/dqqkYH929nqsK This provides PL310 Level 2 Cache Controller Device Tree support for all u8500 based devices. Signed-off-by: Lee Jones --- arch/arm/boot/dts/db8500.dtsi | 8 ++++++++ arch/arm/mach-ux500/cache-l2x0.c | 7 ++++++- 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 9b5e06e..6ae7f69 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -29,6 +29,14 @@ <0xa0410100 0x100>; }; + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = <0 13 4>; + cache-unified; + cache-level = <2>; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <7>; diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index da5569d..77a75ed 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -5,6 +5,8 @@ */ #include +#include + #include #include #include @@ -45,7 +47,10 @@ static int __init ux500_l2x0_init(void) ux500_l2x0_unlock(); /* 64KB way size, 8 way associativity, force WA */ - l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); + if (of_have_populated_dt()) + l2x0_of_init(0x3e060000, 0xc0000fff); + else + l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); /* * We can't disable l2 as we are in non secure mode, currently