From patchwork Wed May 16 02:33:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob X-Patchwork-Id: 8663 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C7CA823E37 for ; Wed, 16 May 2012 02:33:44 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7B773A188FD for ; Wed, 16 May 2012 02:33:44 +0000 (UTC) Received: by yenq6 with SMTP id q6so318914yen.11 for ; Tue, 15 May 2012 19:33:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=oEBcbHJVVX4C12ofwmUMydZ2q7SPAsEa3L1p75ozKQM=; b=G7k0mv20XRFUtzJInYi1OGihOfy30KbNL0AemFDB1XHreG3Cg76xZbSGZOwflFeUij qaTuUIDuegkzJ7U00XiGd+AjGnqNGlZTbG9QaDqGBAlW9DlObOhKsIXS9xIiiAnPDW8j VaPf1oQQrzw/+aPFoFeqCU/If6D/mRkmehP8SNm248O0LLTV0uhpvcpUYvjMUfGdlrZ6 dRP11oRw8VPxY02rdT/7VS13W9eEt4I0wlr26U34EjySb8V61Nh4t/tspM1t6i3rWU7q 4rBg5QtZVkg3vAdQdv748hqZo+8yVLh5UPfvStZTHBhMuKYre2251tJDRmLmeCx4P86P tAfw== Received: by 10.50.87.227 with SMTP id bb3mr659236igb.57.1337135623784; Tue, 15 May 2012 19:33:43 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp460612ibd; Tue, 15 May 2012 19:33:43 -0700 (PDT) Received: by 10.236.187.68 with SMTP id x44mr1388673yhm.129.1337135622738; Tue, 15 May 2012 19:33:42 -0700 (PDT) Received: from mail-yw0-f44.google.com (mail-yw0-f44.google.com [209.85.213.44]) by mx.google.com with ESMTPS id y5si958370yha.116.2012.05.15.19.33.42 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 15 May 2012 19:33:42 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.213.44 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) client-ip=209.85.213.44; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.213.44 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) smtp.mail=rob.lee@linaro.org Received: by yhq56 with SMTP id 56so311839yhq.17 for ; Tue, 15 May 2012 19:33:42 -0700 (PDT) Received: by 10.236.125.234 with SMTP id z70mr1515347yhh.18.1337135622408; Tue, 15 May 2012 19:33:42 -0700 (PDT) Received: from localhost.localdomain ([216.59.27.28]) by mx.google.com with ESMTPS id a68sm4346289yhj.22.2012.05.15.19.33.40 (version=SSLv3 cipher=OTHER); Tue, 15 May 2012 19:33:41 -0700 (PDT) From: Robert Lee To: kernel@pengutronix.de Cc: shawn.guo@linaro.org, u.kleine-koenig@pengutronix.de, richard.zhao@freescale.com, amit.kucheria@linaro.org, daniel.lezcano@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linaro-dev@lists.linaro.org, patches@linaro.org, jj@chaosbits.net Subject: [PATCH v4 1/7] ARM: imx: Modify IMX_IO_P2V macro Date: Tue, 15 May 2012 21:33:30 -0500 Message-Id: <1337135616-8988-2-git-send-email-rob.lee@linaro.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1337135616-8988-1-git-send-email-rob.lee@linaro.org> References: <1337135616-8988-1-git-send-email-rob.lee@linaro.org> X-Gm-Message-State: ALoCoQko63Db1N5DA275yUvLXEXc/yB11PfZm+HN1x8gFM/DZg/h6864WpwMW50a6Yzmk40CWbjR A change is needed in the IMX_IO_P2V macro to allow all imx5 platforms to use common definitions when accessing registers of peripherals on the AIPS2 bus. With this change, IMX_IO_P2V(MX50_AIPS2_BASE_ADDR) == IMX_IO_P2V(MX51_AIPS2_BASE_ADDR) == IMX_IO_P2V(MX53_AIPS2_BASE_ADDR). This change was tested for mapping conflicts using the iop2v script found at git://git.pengutronix.de/git/ukl/imx-iop2v.git and by performing a bootup of a default build using imx_v6_v7_defconfig on a imx51 babbage board and imx53 loco board. The comments were modified to reflect the output given by the script which shows the virtual address mappings. Signed-off-by: Robert Lee --- arch/arm/plat-mxc/include/mach/hardware.h | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 0630513..071afd0 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -50,7 +50,7 @@ * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 * mx21: * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 - * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 * mx25: * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 @@ -58,47 +58,50 @@ * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 * mx27: * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 - * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 * mx31: * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 - * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 * mx35: * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 - * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 * mx50: * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx51: - * TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000 + * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 + * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 - * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000 * mx53: * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 + * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx6q: - * SCU 0x00a00000+0x001000 -> 0xf4000000+0x001000 + * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000 * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 - * ANATOP 0x020c8000+0x001000 -> 0xf42c8000+0x001000 + * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 */ #define IMX_IO_P2V(x) ( \ - 0xf4000000 + \ + (((x) & 0x80000000) >> 7) | \ + (0xf4000000 + \ (((x) & 0x50000000) >> 6) + \ (((x) & 0x0b000000) >> 4) + \ - (((x) & 0x000fffff))) + (((x) & 0x000fffff)))) #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))