From patchwork Tue Nov 27 19:15:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13242 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EE9E023E17 for ; Tue, 27 Nov 2012 19:15:53 +0000 (UTC) Received: from mail-ia0-f180.google.com (mail-ia0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id A11B2A18978 for ; Tue, 27 Nov 2012 19:15:53 +0000 (UTC) Received: by mail-ia0-f180.google.com with SMTP id t4so6349398iag.11 for ; Tue, 27 Nov 2012 11:15:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=GMcrWkgKT8YK3Jd9pMnwnXEV+UAtdN6AKNgh9Ja5KYc=; b=VZTMpi3ZUOdPiuwqnMuZqonVLIttZyh95NcXxLOOXGy4JEJrjHsBYYJTfESk3+9ABA D4iq0t+XpQrPdNyPCHbdwZI7roqEK+ISJdXy8/kBlCX7bBsn6GyZx6xTI2S/UdwKVr/G 9HRCZui+0nYrebzhmHR8fCxkraBGKMuFCmQV5NY12HPR+IHffESf/vjxE0GgjGRxBXtH UYDXbdJ7Z4viVPUmRt1akL108jHgCDEoBPUAp8wwwbCBnbR/NI9XZGQh8OSzXZFL4R4U MRpbFsf9JEiGUBEcJKduaIPre+TT8ZzYPIxgFHhO+sQTU47CUkhRPf7svcRRF/F5YTPA 6Hgw== Received: by 10.43.125.133 with SMTP id gs5mr14751907icc.54.1354043752987; Tue, 27 Nov 2012 11:15:52 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp522462igt; Tue, 27 Nov 2012 11:15:52 -0800 (PST) Received: by 10.14.173.65 with SMTP id u41mr15386330eel.13.1354043751532; Tue, 27 Nov 2012 11:15:51 -0800 (PST) Received: from eu1sys200aog116.obsmtp.com (eu1sys200aog116.obsmtp.com [207.126.144.141]) by mx.google.com with SMTP id i42si38317728eem.16.2012.11.27.11.15.42 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 27 Nov 2012 11:15:51 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.141 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.141; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.141 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKULURXgDmvfXS/80ibFhe6/UoMlZljfk0@postini.com; Tue, 27 Nov 2012 19:15:51 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id D06DA50; Tue, 27 Nov 2012 19:14:48 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 67DFB6D; Tue, 27 Nov 2012 14:16:48 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id D27A124C2C0; Tue, 27 Nov 2012 20:15:14 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 27 Nov 2012 20:15:23 +0100 From: Linus Walleij To: , Mike Turquette , Mike Turquette Cc: Lee Jones , Anmar Oueja , Linus Walleij , Ulf Hansson , Philippe Begnic Subject: [PATCH] clk: ux500: fix bit error Date: Tue, 27 Nov 2012 20:15:20 +0100 Message-ID: <1354043720-30850-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmED+dv8hOviCootg0tYLu272NYjybH/BeFsbeBKtRtsy3sTuLWyc5npUiHdAyHpW92wYnB From: Linus Walleij This fixes a bit error in the U8500 clock implementation: the unused p2_pclk12 registered at bit 12 in periphereral group 6 was defined as using bit 11 rather than bit 12. When walking over and disabling the unused clocks in the tree at late init time, p2_pclk12 was disabled, by effectively clearing the but for p2_pclk11 instead of bit 12 as it should have, thus disabling gpio block 6 and 7. Reported-by: Lee Jones Cc: Ulf Hansson Cc: Philippe Begnic Signed-off-by: Linus Walleij --- Mike if this gets ACKed (beware of more mistakes from this coder) it should go into v3.7 or if that fails be tagged with Cc: stable@kernel.org. --- drivers/clk/ux500/u8500_clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index fb9f291..20ecaa7 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -317,7 +317,7 @@ void u8500_clk_init(void) clk_register_clkdev(clk, NULL, "gpioblock1"); clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE, - BIT(11), 0); + BIT(12), 0); clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, BIT(0), 0);