From patchwork Mon Feb 11 17:10:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 14742 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5BE3023DEA for ; Mon, 11 Feb 2013 17:11:21 +0000 (UTC) Received: from mail-ve0-f169.google.com (mail-ve0-f169.google.com [209.85.128.169]) by fiordland.canonical.com (Postfix) with ESMTP id EC3EAA196F1 for ; Mon, 11 Feb 2013 17:11:20 +0000 (UTC) Received: by mail-ve0-f169.google.com with SMTP id 15so5462242vea.0 for ; Mon, 11 Feb 2013 09:11:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=5BqIteIfuaP+XAZaM9NDtWXG8HxQIGzR4YYzf4Bcohs=; b=k+dLf3VDA1LB/pPUqeVzwuijnDD/1QNOvCDdB3j11eBW04Pq+7GeDXnoA4lou/loUA Q1Nz7WcHO9wJElWZdqmkChp3dthDEQF7KXhTllN4jrprSfIsmocQ7vC2beZ15JNauq2P jG3FNPgWc8bVn1wYMv6nGWBt8qEz0bZTZVcvEFKDUqbSt34Mc3WrKOcblmUxvKnFgtsR 0hu521/bfl8oyolGevKImVt1YpxOYtKSTsbJYHQbWG/ahC9V4yjPt/7U3K8yWQNdINL6 CpnqBcHqfkX9gfzV0R/YTU9AEVez2MbkrYxdFaQrXnc1Eehun0NGY8GtV5nqREYRT6nl 4dXQ== X-Received: by 10.52.75.65 with SMTP id a1mr3244774vdw.79.1360602680378; Mon, 11 Feb 2013 09:11:20 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.252.8 with SMTP id zo8csp107975vec; Mon, 11 Feb 2013 09:11:19 -0800 (PST) X-Received: by 10.50.108.145 with SMTP id hk17mr12983447igb.51.1360602678508; Mon, 11 Feb 2013 09:11:18 -0800 (PST) Received: from mail-pa0-f47.google.com (mail-pa0-f47.google.com [209.85.220.47]) by mx.google.com with ESMTPS id bf6si50554877pab.141.2013.02.11.09.11.17 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 11 Feb 2013 09:11:18 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.47 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) client-ip=209.85.220.47; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.47 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) smtp.mail=haojian.zhuang@linaro.org Received: by mail-pa0-f47.google.com with SMTP id bj3so3104893pad.20 for ; Mon, 11 Feb 2013 09:11:17 -0800 (PST) X-Received: by 10.66.82.103 with SMTP id h7mr42890457pay.6.1360602677759; Mon, 11 Feb 2013 09:11:17 -0800 (PST) Received: from localhost.localdomain ([27.115.121.35]) by mx.google.com with ESMTPS id m3sm67935973pav.4.2013.02.11.09.11.12 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 11 Feb 2013 09:11:16 -0800 (PST) From: Haojian Zhuang To: shiraz.hashim@st.com, shiraz.linux.kernel@gmail.com, linux@arm.linux.org.uk, tony@atomide.com, linux-arm-kernel@lists.infradead.org, swarren@nvidia.com, grant.likely@secretlab.ca, linus.walleij@linaro.org Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v8 01/12] gpio: add gpio offset in gpio range cells property Date: Tue, 12 Feb 2013 01:10:48 +0800 Message-Id: <1360602659-4774-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360602659-4774-1-git-send-email-haojian.zhuang@linaro.org> References: <1360602659-4774-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQlHpWirRTxyhIrQCaReSaMhKiDdSD6rwjkOnz0HTTqgDeODbIqVub5qMwqg1w2/lWxsFEUX Add gpio offset into "gpio-range-cells" property. It's used to support sparse pinctrl range in gpio chip. Signed-off-by: Haojian Zhuang Acked-by: Viresh Kumar Acked-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio.txt | 6 +++--- arch/arm/boot/dts/spear1310.dtsi | 4 ++-- arch/arm/boot/dts/spear1340.dtsi | 4 ++-- arch/arm/boot/dts/spear310.dtsi | 4 ++-- arch/arm/boot/dts/spear320.dtsi | 4 ++-- drivers/gpio/gpiolib-of.c | 15 ++------------- 6 files changed, 13 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index a336287..d933af3 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example, compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; reg = <0x1460 0x18>; gpio-controller; - gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; + gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; } @@ -107,8 +107,8 @@ where, Next values specify the base pin and number of pins for the range handled by 'qe_pio_e' gpio. In the given example from base pin 20 to - pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled - by this gpio controller. + pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under + pinctrl2 with gpio offset 10 is handled by this gpio controller. The pinctrl node must have "#gpio-range-cells" property to show number of arguments to pass with phandle from gpio controllers node. diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi index 1513c19..122ae94 100644 --- a/arch/arm/boot/dts/spear1310.dtsi +++ b/arch/arm/boot/dts/spear1310.dtsi @@ -89,7 +89,7 @@ pinmux: pinmux@e0700000 { compatible = "st,spear1310-pinmux"; reg = <0xe0700000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; apb { @@ -212,7 +212,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 246>; + gpio-ranges = <&pinmux 0 0 246>; status = "disabled"; st-plgpio,ngpio = <246>; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index b2d41b7..7ec1eb8 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -63,7 +63,7 @@ pinmux: pinmux@e0700000 { compatible = "st,spear1340-pinmux"; reg = <0xe0700000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; pwm: pwm@e0180000 { @@ -146,7 +146,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 252>; + gpio-ranges = <&pinmux 0 0 252>; status = "disabled"; st-plgpio,ngpio = <250>; diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index ab45b8c..9537208 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi @@ -25,7 +25,7 @@ pinmux: pinmux@b4000000 { compatible = "st,spear310-pinmux"; reg = <0xb4000000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; fsmc: flash@44000000 { @@ -102,7 +102,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 102>; + gpio-ranges = <&pinmux 0 0 102>; status = "disabled"; st-plgpio,ngpio = <102>; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index caa5520..ffea342 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -24,7 +24,7 @@ pinmux: pinmux@b3000000 { compatible = "st,spear320-pinmux"; reg = <0xb3000000 0x1000>; - #gpio-range-cells = <2>; + #gpio-range-cells = <3>; }; clcd@90000000 { @@ -130,7 +130,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 102>; + gpio-ranges = <&pinmux 0 0 102>; status = "disabled"; st-plgpio,ngpio = <102>; diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 25b1dbe..380f84e 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -238,22 +238,11 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) if (!pctldev) break; - /* - * This assumes that the n GPIO pins are consecutive in the - * GPIO number space, and that the pins are also consecutive - * in their local number space. Currently it is not possible - * to add different ranges for one and the same GPIO chip, - * as the code assumes that we have one consecutive range - * on both, mapping 1-to-1. - * - * TODO: make the OF bindings handle multiple sparse ranges - * on the same GPIO chip. - */ ret = gpiochip_add_pin_range(chip, pinctrl_dev_get_devname(pctldev), - 0, /* offset in gpiochip */ pinspec.args[0], - pinspec.args[1]); + pinspec.args[1], + pinspec.args[2]); if (ret) break;