From patchwork Thu Feb 28 07:19:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 15136 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A90EA23E2E for ; Thu, 28 Feb 2013 07:20:02 +0000 (UTC) Received: from mail-ve0-f169.google.com (mail-ve0-f169.google.com [209.85.128.169]) by fiordland.canonical.com (Postfix) with ESMTP id 572FDA18EE6 for ; Thu, 28 Feb 2013 07:20:02 +0000 (UTC) Received: by mail-ve0-f169.google.com with SMTP id 15so1490912vea.28 for ; Wed, 27 Feb 2013 23:20:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=Gr42dPSYbwJtpG9TveLGzWyjInBOERA/FTr9Rza8Qkk=; b=SgMwDfL2SyvKGUvF0DBX85ECRHvsKo3DcXOVTyWpOZTJGA6Sp8O4PQ55ubxB3aFRtr yjmqVQ7n/bHtd9OWp9iJ3+gtKnxdYmiyVjC2TgEMB9BiosV6wCVHnSJaMm729bjxgz1M JnsKLEJ5j5DmMrDVOAG8mruXA7VNb/K4Z+ZLMCyZY7f3hj0jC6DMvj9bU8DKsQOe/DNh y5da/fm5KxazpSBk8gMw8u+Xv1pn4xIlLKxVg2ZxGMNbPfhAJz0OmSe348hz7aQ4JaI3 mdJ5DYoo9AkSWF1QJX5CEbcZQxRb7BASLxUP3Jj04HOoFts0//nGuoALTIxqwZv/eKDq giNA== X-Received: by 10.58.181.201 with SMTP id dy9mr2180070vec.34.1362036001842; Wed, 27 Feb 2013 23:20:01 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp210886veb; Wed, 27 Feb 2013 23:20:01 -0800 (PST) X-Received: by 10.66.158.230 with SMTP id wx6mr11595024pab.147.1362036000916; Wed, 27 Feb 2013 23:20:00 -0800 (PST) Received: from mail-pa0-f43.google.com (mail-pa0-f43.google.com [209.85.220.43]) by mx.google.com with ESMTPS id rf10si3919881pbc.96.2013.02.27.23.20.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 23:20:00 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.43 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) client-ip=209.85.220.43; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.43 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) smtp.mail=haojian.zhuang@linaro.org Received: by mail-pa0-f43.google.com with SMTP id bh2so977931pad.30 for ; Wed, 27 Feb 2013 23:20:00 -0800 (PST) X-Received: by 10.66.162.41 with SMTP id xx9mr11853066pab.168.1362036000543; Wed, 27 Feb 2013 23:20:00 -0800 (PST) Received: from localhost.localdomain ([140.206.155.71]) by mx.google.com with ESMTPS id k7sm8255069paz.13.2013.02.27.23.19.55 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 23:19:59 -0800 (PST) From: Haojian Zhuang To: jone.lixin@huawei.com, arnd@arndb.de, olof@lixom.net, linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH 5/7] document: append hisilicon clock binding Date: Thu, 28 Feb 2013 15:19:24 +0800 Message-Id: <1362035966-17628-5-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1362035966-17628-1-git-send-email-haojian.zhuang@linaro.org> References: <1362035966-17628-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQk4F+hpqmL1425hlh/QGi9tccbgKuGhXjymyEpDLJVCmpOUOZ3l5sIUcXgrUktwUsr+wSwY Add hisilicon clock binding document for device tree. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/clock/hisilicon.txt | 73 ++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hisilicon.txt diff --git a/Documentation/devicetree/bindings/clock/hisilicon.txt b/Documentation/devicetree/bindings/clock/hisilicon.txt new file mode 100644 index 0000000..04fefc3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hisilicon.txt @@ -0,0 +1,73 @@ +Device Tree Clock bindings for arch-vt8500 + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties for mux clocks: + - compatible : Shall be "hisilicon,hi3620-clk-mux". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,hi3620-mux : array of mux register offset & mask bits + +Required properties for Hi3620 gate clocks: + - compatible : Shall be "hisilicon,hi3620-clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,hi3620-clkgate : array of enable register offset & enable bit + - hisilicon,hi3620-clkreset : array of reset register offset & enable bit + +Required properties for gate clocks: + - compatible : Shall be "hisilicon,clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,clkgate-inverted : bool value. True means that set-to-disable. + +Required properties for clock divider: + - compatible : Shall be "hisilicon,clk-div-table". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - #hisilicon,clkdiv-table-cells : the number of parameters after phandle in + hisilicon,clkdiv-table property. + - hisilicon,clkdiv-table : list of value that are used to configure clock + divider. They're value of phandle, index & divider value. + - hisilicon,clkdiv : array of divider register offset & mask bits. + +Required properties for clock fixed factor divider: + - compatible : Shall be "hisilicon,fixed-factor". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,fixed-factor : array of multiplier & divider. + +For example: + timclk1: clkgate@38 { + compatible = "hisilicon,clk-gate"; + #clock-cells = <0>; + clocks = <&refclk_timer1>; + clock-output-names = "timclk1"; + hisilicon,clkgate-inverted; + hisilicon,clkgate = <0 18>; + }; + + dtable: clkdiv@0 { + #hisilicon,clkdiv-table-cells = <2>; + }; + + div_cfgaxi: clkdiv@2 { + compatible = "hisilicon,clk-div-table"; + #clock-cells = <0>; + clocks = <&div_shareaxi>; + clock-output-names = "cfgAXI_div"; + hisilicon,clkdiv-table = <&dtable 0x01 2>; + hisilicon,clkdiv = <0x100 0x60>; + };