From patchwork Thu May 23 09:45:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 17108 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f200.google.com (mail-vc0-f200.google.com [209.85.220.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9BFD12395B for ; Thu, 23 May 2013 09:47:06 +0000 (UTC) Received: by mail-vc0-f200.google.com with SMTP id hr11sf3965301vcb.7 for ; Thu, 23 May 2013 02:46:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-beenthere:x-forwarded-to:x-forwarded-for:delivered-to:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe :content-type; bh=+Js02znHeeEx74AhwBCm1fQYbmSsT8amEWKgHu7WNJU=; b=k2TuLDfFt9fIUB+e9V/Za67mw8gX8Wqb84Q3WvsPPfqMZK9XSqv9/Ur5rY2bk3oyt9 m9w65kbXFKAxLqjJC6UdsC6QneX+ub51MuIYYGS5sOiSNnqKy/aDRKR7cQ5nh6dTDgB2 leWXGr8mKVBJuj3TwF8Fq5vfMig/Jh/Lbjx2vh2aJoFtUk/6RCY5uJd+iRv/BwqvuRsM GdwOcRBr/A1PJ1XuQGP5tNwZlWb6afy0mmaeKX0g4IV+rHSiaetvRJhOrrB/pRqOE9s0 opQMZ68vwoXzAMrMH0mxxCI0eAP3T2c+/hnGFyhXCDvhK9CKeB9Sj+8jYhVBBoo2P4q0 bSLQ== X-Received: by 10.224.174.145 with SMTP id t17mr5966439qaz.4.1369302371772; Thu, 23 May 2013 02:46:11 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.36.9 with SMTP id m9ls1234237qej.55.gmail; Thu, 23 May 2013 02:46:11 -0700 (PDT) X-Received: by 10.52.101.163 with SMTP id fh3mr3941128vdb.107.1369302371594; Thu, 23 May 2013 02:46:11 -0700 (PDT) Received: from mail-vb0-x22d.google.com (mail-vb0-x22d.google.com [2607:f8b0:400c:c02::22d]) by mx.google.com with ESMTPS id zt2si4805357vdb.128.2013.05.23.02.46.11 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 May 2013 02:46:11 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c02::22d is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c02::22d; Received: by mail-vb0-f45.google.com with SMTP id 12so2019991vbf.32 for ; Thu, 23 May 2013 02:46:11 -0700 (PDT) X-Received: by 10.58.225.228 with SMTP id rn4mr4630978vec.35.1369302371386; Thu, 23 May 2013 02:46:11 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.126.138 with SMTP id c10csp42017vcs; Thu, 23 May 2013 02:46:10 -0700 (PDT) X-Received: by 10.15.93.193 with SMTP id w41mr29779354eez.22.1369302367601; Thu, 23 May 2013 02:46:07 -0700 (PDT) Received: from eu1sys200aog116.obsmtp.com (eu1sys200aog116.obsmtp.com [207.126.144.141]) by mx.google.com with SMTP id v46si14825003een.17.2013.05.23.02.45.40 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 23 May 2013 02:46:07 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.141 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.141; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKUZ3lP4OcDGPvr4f0ruwYxmsr2IH1C2g8@postini.com; Thu, 23 May 2013 09:46:07 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2684211C; Thu, 23 May 2013 09:45:35 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E47142D09; Thu, 23 May 2013 09:45:19 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 1C81124C2E5; Thu, 23 May 2013 11:45:29 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.279.5; Thu, 23 May 2013 11:45:34 +0200 From: Ulf Hansson To: , Russell King Cc: , Chris Ball , Daniel Lezcano , Linus Walleij , Rickard Andersson , Ulf Hansson , Johan Rudholm Subject: [PATCH V2 2/3] mmc: mmci: Adapt to register write restrictions Date: Thu, 23 May 2013 11:45:06 +0200 Message-ID: <1369302307-28540-3-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com> References: <1369302307-28540-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmCp9XTxV1N3gcJ3TPPBKXMSkfsRgsCJSA0H0oglHXhr/r9/SbQ1c+mDU9sqMFMNsr07oB7 X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::22d is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Ulf Hansson After a write to the MMCICLOCK register data cannot be written to this register for three feedback clock cycles. Writes to the MMCIPOWER register must be separated by three MCLK cycles. Previously no issues has been observered, but using higher ARM clock frequencies on STE- platforms has triggered this problem. The MMCICLOCK register is written to in .set_ios and for some data transmissions for SDIO. We do not need a delay at the data transmission path, because sending and receiving data will require more than three clock cycles. Then we use a simple logic to only delay in .set_ios and thus we don't affect throughput performance. Signed-off-by: Ulf Hansson Signed-off-by: Johan Rudholm --- Changes in v2: None --- drivers/mmc/host/mmci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 9fa8855..8f70e5b 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -189,6 +189,21 @@ static int mmci_validate_data(struct mmci_host *host, return 0; } +static void mmci_reg_delay(struct mmci_host *host) +{ + /* + * According to the spec, at least three feedback clock cycles + * of max 52 MHz must pass between two writes to the MMCICLOCK reg. + * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. + * Worst delay time during card init is at 100 kHz => 30 us. + * Worst delay time when up and running is at 25 MHz => 120 ns. + */ + if (host->cclk < 20000000) + udelay(30); + else + ndelay(120); +} + /* * This must be called with host->lock held */ @@ -1264,6 +1279,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) mmci_set_clkreg(host, ios->clock); mmci_write_pwrreg(host, pwr); + mmci_reg_delay(host); spin_unlock_irqrestore(&host->lock, flags);