From patchwork Mon Jun 3 09:30:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 17435 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f200.google.com (mail-wi0-f200.google.com [209.85.212.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1E4B323916 for ; Mon, 3 Jun 2013 09:32:17 +0000 (UTC) Received: by mail-wi0-f200.google.com with SMTP id c10sf2972222wiw.3 for ; Mon, 03 Jun 2013 02:32:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=rthLLURgNun98HDPnkZ3Oyko/0bCm4FNkkMEJwlGUl4=; b=IPHRoXVqoCiuTeAsvxM76Uy1IqLJjXwRqpslhYLywUS2ZZFjJX1xLHMlL6ia5n81Eh TF/YyC6xddGl93Bi/ck0nN97tVbyuamTb4EHSVwHWD02NzCuvtAylXKdVBFiveTYAcFy yvWf30/gDfaXsvFgWu1Q3u4ViemDPWug82f7Uv1zQL2AWKHd4A0wP/2jr9xwxHzOIw4O FH+TauzzReK5YDA+V/97vDELS8GGyR3rw+l0z402b+mo2A35Zr1Tfi4YqSm1mOwBPgnF hsF0g1DVwW1xlZz9a2rdMxC6mPgF73eaFy77S8wXtAvZ23kT+DLirk+CZUHWVMCIgoKp 8TnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=rthLLURgNun98HDPnkZ3Oyko/0bCm4FNkkMEJwlGUl4=; b=fbVHy0pZCOtrgWWeIMTRFG3YTjV7r/EscnCX6PoHnb+20x/1rIaTclhj+hXM2r9Gb0 fG8QETWqEycpmQ+5pH2c5LkUiGA6C/rK/x/krpqoSMudkQZBZp1JxctkVLxbftRZliCn 7gu0d5WoeANDPkQSANLXw/FrJci9+QOXU/S2138z37NulFXSsEPEXQHawukHn7J/uO8f pUi00fBfocggGk2RUsbsMnkXt2yffS0/mU7VwgQN9OGg6qRCKBIRbqLBtZdnYO4oG35U kDXS0UEE+1Tv5y2sUEzKLi3ONXiJCQ2XmoyuL41ne6OgVxr6QV34Nq914ifhIo5rScyA IfZw== X-Received: by 10.180.12.200 with SMTP id a8mr4513999wic.1.1370251936114; Mon, 03 Jun 2013 02:32:16 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.180.82.68 with SMTP id g4ls778844wiy.41.canary; Mon, 03 Jun 2013 02:32:15 -0700 (PDT) X-Received: by 10.194.243.129 with SMTP id wy1mr7423671wjc.47.1370251935915; Mon, 03 Jun 2013 02:32:15 -0700 (PDT) Received: from mail-ve0-x22e.google.com (mail-ve0-x22e.google.com [2607:f8b0:400c:c01::22e]) by mx.google.com with ESMTPS id dm1si18302596wjb.74.2013.06.03.02.32.15 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 03 Jun 2013 02:32:15 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c01::22e is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c01::22e; Received: by mail-ve0-f174.google.com with SMTP id oz10so2610500veb.5 for ; Mon, 03 Jun 2013 02:32:14 -0700 (PDT) X-Received: by 10.58.144.231 with SMTP id sp7mr16779317veb.34.1370251934729; Mon, 03 Jun 2013 02:32:14 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.10.206 with SMTP id pb14csp71061vcb; Mon, 3 Jun 2013 02:32:14 -0700 (PDT) X-Received: by 10.68.113.165 with SMTP id iz5mr23118721pbb.116.1370251933876; Mon, 03 Jun 2013 02:32:13 -0700 (PDT) Received: from mail-pd0-f171.google.com (mail-pd0-f171.google.com [209.85.192.171]) by mx.google.com with ESMTPS id px9si22591001pbb.155.2013.06.03.02.32.12 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 03 Jun 2013 02:32:13 -0700 (PDT) Received-SPF: pass (google.com: domain of haojian.zhuang@gmail.com designates 209.85.192.171 as permitted sender) client-ip=209.85.192.171; Received: by mail-pd0-f171.google.com with SMTP id z11so5426654pdj.16 for ; Mon, 03 Jun 2013 02:32:12 -0700 (PDT) X-Received: by 10.66.87.5 with SMTP id t5mr2172657paz.169.1370251932743; Mon, 03 Jun 2013 02:32:12 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id wi6sm58333510pbc.22.2013.06.03.02.32.07 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 03 Jun 2013 02:32:11 -0700 (PDT) From: Haojian Zhuang To: tglx@linutronix.de, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, chao.xie@marvell.com, john.stultz@linaro.org, mturquette@linaro.org, eric.y.miao@gmail.com Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v3 05/11] irqchip: mmp: avoid to include irqs head file Date: Mon, 3 Jun 2013 17:30:39 +0800 Message-Id: <1370251845-31373-6-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370251845-31373-1-git-send-email-haojian.zhuang@gmail.com> References: <1370251845-31373-1-git-send-email-haojian.zhuang@gmail.com> X-Gm-Message-State: ALoCoQmjIUC8QRjCLndipDusVAd+xQZwvbL2uXJAiB21lIQicKhL3FoWaeF8P52m3TwNjQAmQi20 X-Original-Sender: haojian.zhuang@gmail.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22e is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gmail.com Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Since in irq-mmp.c blocks the multiplatform build, remove it instead. Signed-off-by: Haojian Zhuang --- drivers/irqchip/irq-mmp.c | 45 +++++++++++++++++++++------------------------ 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c index 1f81432..2cb7cd0 100644 --- a/drivers/irqchip/irq-mmp.c +++ b/drivers/irqchip/irq-mmp.c @@ -24,8 +24,6 @@ #include #include -#include - #include "irqchip.h" #define MAX_ICU_NR 16 @@ -249,7 +247,7 @@ void __init icu_init_irq(void) /* MMP2 (ARMv7) */ void __init mmp2_init_icu(void) { - int irq; + int irq, end; max_icu_nr = 8; mmp_icu_base = ioremap(0xd4282000, 0x1000); @@ -263,11 +261,12 @@ void __init mmp2_init_icu(void) &icu_data[0]); icu_data[1].reg_status = mmp_icu_base + 0x150; icu_data[1].reg_mask = mmp_icu_base + 0x168; - icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; - icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; + icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base + + icu_data[0].nr_irqs; + icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */ icu_data[1].nr_irqs = 2; icu_data[1].cascade_irq = 4; - icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; + icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs; icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, icu_data[1].virq_base, 0, &irq_domain_simple_ops, @@ -276,7 +275,7 @@ void __init mmp2_init_icu(void) icu_data[2].reg_mask = mmp_icu_base + 0x16c; icu_data[2].nr_irqs = 2; icu_data[2].cascade_irq = 5; - icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; + icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs; icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, icu_data[2].virq_base, 0, &irq_domain_simple_ops, @@ -285,7 +284,7 @@ void __init mmp2_init_icu(void) icu_data[3].reg_mask = mmp_icu_base + 0x17c; icu_data[3].nr_irqs = 3; icu_data[3].cascade_irq = 9; - icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; + icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs; icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, icu_data[3].virq_base, 0, &irq_domain_simple_ops, @@ -294,7 +293,7 @@ void __init mmp2_init_icu(void) icu_data[4].reg_mask = mmp_icu_base + 0x170; icu_data[4].nr_irqs = 5; icu_data[4].cascade_irq = 17; - icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; + icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs; icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, icu_data[4].virq_base, 0, &irq_domain_simple_ops, @@ -303,7 +302,7 @@ void __init mmp2_init_icu(void) icu_data[5].reg_mask = mmp_icu_base + 0x174; icu_data[5].nr_irqs = 15; icu_data[5].cascade_irq = 35; - icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; + icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs; icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, icu_data[5].virq_base, 0, &irq_domain_simple_ops, @@ -312,7 +311,7 @@ void __init mmp2_init_icu(void) icu_data[6].reg_mask = mmp_icu_base + 0x178; icu_data[6].nr_irqs = 2; icu_data[6].cascade_irq = 51; - icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; + icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs; icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, icu_data[6].virq_base, 0, &irq_domain_simple_ops, @@ -321,28 +320,26 @@ void __init mmp2_init_icu(void) icu_data[7].reg_mask = mmp_icu_base + 0x184; icu_data[7].nr_irqs = 2; icu_data[7].cascade_irq = 55; - icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; + icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs; icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, icu_data[7].virq_base, 0, &irq_domain_simple_ops, &icu_data[7]); - for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) { + end = icu_data[7].virq_base + icu_data[7].nr_irqs; + for (irq = 0; irq < end; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - switch (irq) { - case IRQ_MMP2_PMIC_MUX: - case IRQ_MMP2_RTC_MUX: - case IRQ_MMP2_KEYPAD_MUX: - case IRQ_MMP2_TWSI_MUX: - case IRQ_MMP2_MISC_MUX: - case IRQ_MMP2_MIPI_HSI1_MUX: - case IRQ_MMP2_MIPI_HSI0_MUX: + if (irq == icu_data[1].cascade_irq || + irq == icu_data[2].cascade_irq || + irq == icu_data[3].cascade_irq || + irq == icu_data[4].cascade_irq || + irq == icu_data[5].cascade_irq || + irq == icu_data[6].cascade_irq || + irq == icu_data[7].cascade_irq) { irq_set_chip(irq, &icu_irq_chip); irq_set_chained_handler(irq, icu_mux_irq_demux); - break; - default: + } else { irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); - break; } set_irq_flags(irq, IRQF_VALID); }