From patchwork Tue Sep 3 12:04:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 19707 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f70.google.com (mail-qa0-f70.google.com [209.85.216.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1ABF424869 for ; Tue, 3 Sep 2013 12:04:56 +0000 (UTC) Received: by mail-qa0-f70.google.com with SMTP id ii20sf3185546qab.9 for ; Tue, 03 Sep 2013 05:04:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=fqTI80BpDtB35B/DDlwcV6abYaPSTJih91OvWixdzDY=; b=ZSW74ZDmW1FKoh6RHlxKsN47U6gSNnK1oz2fidCDy6mT8JzIxThU/sia+wz46Mwr0Z 5q5eQsm778aqWea+5dN4Wvt6gJ4SwLlCAwpCR4K7sNJnIzLPg/BfQXOnem8PI0gLFIBa tEImVKhAfIEiLJEXZKBfW7PTyxzYqdLQZJWog9adPxpR4zDMln2+Luhdscru13VfmDqW TNqacBtK5mopVDA+MRtdsvAti33r0d/REU+8KYC5JYbzGlbHmG+VHwzlGSdr5Vrd7mDZ gRgpGfbAG+xsSuw0Ngc0dAbDOkT4JSCVsw0xb1E8xg022iIJHdJK9GNAMj20XdYuv/p0 r3bw== X-Received: by 10.58.40.105 with SMTP id w9mr2409562vek.21.1378209895467; Tue, 03 Sep 2013 05:04:55 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.48.41 with SMTP id i9ls647424qen.44.gmail; Tue, 03 Sep 2013 05:04:55 -0700 (PDT) X-Received: by 10.52.229.73 with SMTP id so9mr6723016vdc.27.1378209895313; Tue, 03 Sep 2013 05:04:55 -0700 (PDT) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by mx.google.com with ESMTPS id de6si4370033vcb.34.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 05:04:55 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.175; Received: by mail-ve0-f175.google.com with SMTP id oy10so3819066veb.20 for ; Tue, 03 Sep 2013 05:04:55 -0700 (PDT) X-Gm-Message-State: ALoCoQmSXRXKuDh58WMdIr+baDWiJtDaevxxpD0NX0/cYMwd/uEhfdGj1a8dlvJ+PDVQbQkMk6b8 X-Received: by 10.52.230.102 with SMTP id sx6mr22875850vdc.15.1378209895190; Tue, 03 Sep 2013 05:04:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp167286vcz; Tue, 3 Sep 2013 05:04:54 -0700 (PDT) X-Received: by 10.14.184.3 with SMTP id r3mr4489672eem.49.1378209893696; Tue, 03 Sep 2013 05:04:53 -0700 (PDT) Received: from mail-ea0-f182.google.com (mail-ea0-f182.google.com [209.85.215.182]) by mx.google.com with ESMTPS id f3si14364276eet.209.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 05:04:53 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.215.182 is neither permitted nor denied by best guess record for domain of ulf.hansson@linaro.org) client-ip=209.85.215.182; Received: by mail-ea0-f182.google.com with SMTP id o10so2990416eaj.27 for ; Tue, 03 Sep 2013 05:04:53 -0700 (PDT) X-Received: by 10.14.246.11 with SMTP id p11mr46484585eer.9.1378209893045; Tue, 03 Sep 2013 05:04:53 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id n48sm30911377eeg.17.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 05:04:52 -0700 (PDT) From: Ulf Hansson To: linux-arm-kernel@lists.infradead.org, Russell King Cc: linux-mmc@vger.kernel.org, Chris Ball , Daniel Lezcano , Linus Walleij , Ulf Hansson , Johan Rudholm Subject: [PATCH V4 3/4] mmc: mmci: Adapt to register write restrictions Date: Tue, 3 Sep 2013 14:04:48 +0200 Message-Id: <1378209888-16874-1-git-send-email-ulf.hansson@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ulf.hansson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , After a write to the MMCICLOCK register data cannot be written to this register for three feedback clock cycles. Writes to the MMCIPOWER register must be separated by three MCLK cycles. Previously no issues has been observered, but using higher ARM clock frequencies on STE- platforms has triggered this problem. The MMCICLOCK register is written to in .set_ios and for some data transmissions for SDIO. We do not need a delay at the data transmission path, because sending and receiving data will require more than three clock cycles. Then we use a simple logic to only delay in .set_ios and thus we don't affect throughput performance. Signed-off-by: Johan Rudholm Signed-off-by: Ulf Hansson Acked-by: Rickard Andersson --- Changes in v4: - Fixed typo of 25 MHz instead of 20 MHz --- drivers/mmc/host/mmci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index c550b3e..604e41d 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -189,6 +189,21 @@ static int mmci_validate_data(struct mmci_host *host, return 0; } +static void mmci_reg_delay(struct mmci_host *host) +{ + /* + * According to the spec, at least three feedback clock cycles + * of max 52 MHz must pass between two writes to the MMCICLOCK reg. + * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. + * Worst delay time during card init is at 100 kHz => 30 us. + * Worst delay time when up and running is at 25 MHz => 120 ns. + */ + if (host->cclk < 25000000) + udelay(30); + else + ndelay(120); +} + /* * This must be called with host->lock held */ @@ -1264,6 +1279,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) mmci_set_clkreg(host, ios->clock); mmci_write_pwrreg(host, pwr); + mmci_reg_delay(host); spin_unlock_irqrestore(&host->lock, flags);