From patchwork Fri Oct 18 09:05:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21111 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pb0-f70.google.com (mail-pb0-f70.google.com [209.85.160.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 697AA246F1 for ; Fri, 18 Oct 2013 09:05:41 +0000 (UTC) Received: by mail-pb0-f70.google.com with SMTP id jt11sf5547971pbb.1 for ; Fri, 18 Oct 2013 02:05:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=/7lrAB92Sf4ilueIkhw+TXIDIjyRMfHzeII9/wGbdLM=; b=YtGd/WFckptvtmB/jmopL5yAzkbDkdWkbZ1oq4RolYmqiHbkf5nRod1qvR9c6ShVvg XOdFjk45YKs1KQZ/EgV1R1oV8RZXRvU+f8BXhurpONhYl6ciZvdz9IGvM5XW58qp+Pzr MHtjwMr1FRQKy9iBllzP+DG/Vxg1lc9WJJYH0q0oMiBd+oeChWFPT0X5X5leSZXc3PjH BJJgHKiyWgB1SnmJ+HnReiwHAJBiHTQw7Xw5qEex+p55w3G90N8oRaQO4tyv/yba1mFr RIRilYqhwLzZxu2dwL1m1Vlqt9+K+YWJpOR2+cn/abHjn49x2d2Cv84PEldjJ+A8kTFN WoCg== X-Received: by 10.66.250.233 with SMTP id zf9mr920071pac.12.1382087140691; Fri, 18 Oct 2013 02:05:40 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.81.210 with SMTP id c18ls1338233qey.37.gmail; Fri, 18 Oct 2013 02:05:40 -0700 (PDT) X-Received: by 10.58.136.231 with SMTP id qd7mr1165887veb.1.1382087140521; Fri, 18 Oct 2013 02:05:40 -0700 (PDT) Received: from mail-ve0-f180.google.com (mail-ve0-f180.google.com [209.85.128.180]) by mx.google.com with ESMTPS id zw10si117132vdb.44.2013.10.18.02.05.40 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 18 Oct 2013 02:05:40 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.180; Received: by mail-ve0-f180.google.com with SMTP id db12so1807904veb.39 for ; Fri, 18 Oct 2013 02:05:40 -0700 (PDT) X-Gm-Message-State: ALoCoQnnD9hAnSjxsYJbJxOsnt9JQfF2EufuokdMsYNgoBMP3YfDdoBBMn8QEEive8zRz9QLp99Q X-Received: by 10.58.38.200 with SMTP id i8mr1187474vek.6.1382087140405; Fri, 18 Oct 2013 02:05:40 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp19956vcz; Fri, 18 Oct 2013 02:05:39 -0700 (PDT) X-Received: by 10.180.211.206 with SMTP id ne14mr1544400wic.30.1382087139431; Fri, 18 Oct 2013 02:05:39 -0700 (PDT) Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id km10si181692wjc.153.2013.10.18.02.05.38 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 18 Oct 2013 02:05:39 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=74.125.82.50; Received: by mail-wg0-f50.google.com with SMTP id n12so3438536wgh.29 for ; Fri, 18 Oct 2013 02:05:38 -0700 (PDT) X-Received: by 10.180.98.228 with SMTP id el4mr1573371wib.4.1382087138768; Fri, 18 Oct 2013 02:05:38 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id y20sm1439449wib.0.2013.10.18.02.05.37 for (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128/128); Fri, 18 Oct 2013 02:05:38 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Lee Jones Cc: devicetree@vger.kernel.org, Linus Walleij Subject: [PATCH 5/5] ARM: ux500: register all SSP and SPI blocks Date: Fri, 18 Oct 2013 11:05:34 +0200 Message-Id: <1382087134-31740-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This adds the SSP and SPI blocks to the device tree and makes them active. Only this way can their clocks be properly gated off at boot. Cc: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 75 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index b7d1738..9edc392 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -704,7 +704,80 @@ interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; + clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; + clock-names = "ssp0clk", "apb_pclk"; + dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ + <&dma 8 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + ssp@80003000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80003000 0x1000>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; + clock-names = "ssp1clk", "apb_pclk"; + dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ + <&dma 9 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@8011a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8011a000 0x1000>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; + clock-names = "spi0clk", "apb_pclk"; + dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ + <&dma 0 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@80112000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80112000 0x1000>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; + clock-names = "spi1clk", "apb_pclk"; + dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ + <&dma 35 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@80111000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80111000 0x1000>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; + clock-names = "spi2clk", "apb_pclk"; + dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ + <&dma 33 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@80129000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80129000 0x1000>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; + clock-names = "spi3clk", "apb_pclk"; + dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ + <&dma 40 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; }; uart@80120000 {