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[188.246.204.87]) by mx.google.com with ESMTPSA id d2sm6644929wik.11.2013.12.13.04.06.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Dec 2013 04:06:52 -0800 (PST) From: Steve Capper To: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk, will.deacon@arm.com, catalin.marinas@arm.com, patches@linaro.org, Steve Capper Subject: [PATCH 2/2] arm: cacheflush: Fix user split-caching logic Date: Fri, 13 Dec 2013 12:06:31 +0000 Message-Id: <1386936391-30493-3-git-send-email-steve.capper@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386936391-30493-1-git-send-email-steve.capper@linaro.org> References: <1386936391-30493-1-git-send-email-steve.capper@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: steve.capper@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The user split-caching logic in __do_cache_op divides the area to be flushed into interruptable chunks of size PAGE_SIZE. Unfortunately, there is no check to see whether or not the range to be flushed is smaller than the chunk size. This can result cache flushes for larger ranges than intended, which can result in the flush failing with a -EFAULT. I've observed slowdown and failure with the icache-hygiene test from libhugetlbfs. This patch fixes the problem by replacing chunk with the minimum of PAGE_SIZE or (end - start), thus we do not overflush. Signed-off-by: Steve Capper --- arch/arm/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 8fcda14..5d3c455 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -503,7 +503,7 @@ static inline int __do_cache_op(unsigned long start, unsigned long end) { int ret; - unsigned long chunk = PAGE_SIZE; + unsigned long chunk = min(end - start, PAGE_SIZE); do { if (signal_pending(current)) {