From patchwork Thu Mar 20 09:20:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 26636 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yk0-f198.google.com (mail-yk0-f198.google.com [209.85.160.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5D668202E0 for ; Thu, 20 Mar 2014 09:21:25 +0000 (UTC) Received: by mail-yk0-f198.google.com with SMTP id 9sf3269977ykp.1 for ; Thu, 20 Mar 2014 02:21:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=LvauEDiPYruMci85HJYEeUuNe/GvfYiCe0LQqHkB1l8=; b=D4RWUDvjeoMjH3b0OjRH7gkIqw5Hfg/xPxtk+a+unaEN6p0d9WaHV7tvDWJopTPcfd 2KpjO04lqdX5q3K4ZzFPPBroAvwsQ8r6F77KDmnhVWkdFPr+aPa2NrZHd07LjMESgMtf +Y1MHHkgMdgtJz1j/Ne6XXjckT5jzhA8OxSAFKbf9U2wqMMrVtsS8Eke56ZT2ZmtKorm +9EuXAr32GD1SZ30VUBT+V42aUPF1Pk4GQMa2B12MycvgHUJuS+/1V5Z9a4pBys9dCOj mKrCRD2heiTdcZsIHiJ4U0JXVLNDXcUiEkqdsrMeSxq5j069UIQXi7l4Xd/omdFqNjSM tb+Q== X-Gm-Message-State: ALoCoQlZLGbezxeISMYlWvsf97utfEYNhIOpPfVeNIXx5ulej24quFkGxkRNzvxKyttusdx5n8XG X-Received: by 10.58.46.204 with SMTP id x12mr7385799vem.19.1395307285123; Thu, 20 Mar 2014 02:21:25 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.86.233 with SMTP id p96ls164571qgd.33.gmail; Thu, 20 Mar 2014 02:21:25 -0700 (PDT) X-Received: by 10.221.61.210 with SMTP id wx18mr4399500vcb.27.1395307284981; Thu, 20 Mar 2014 02:21:24 -0700 (PDT) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by mx.google.com with ESMTPS id be7si286969vcb.143.2014.03.20.02.21.24 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:21:24 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.175; Received: by mail-ve0-f175.google.com with SMTP id oz11so591827veb.6 for ; Thu, 20 Mar 2014 02:21:24 -0700 (PDT) X-Received: by 10.220.164.80 with SMTP id d16mr32846324vcy.15.1395307284895; Thu, 20 Mar 2014 02:21:24 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.78.9 with SMTP id i9csp372491vck; Thu, 20 Mar 2014 02:21:24 -0700 (PDT) X-Received: by 10.194.188.41 with SMTP id fx9mr6608388wjc.56.1395307283775; Thu, 20 Mar 2014 02:21:23 -0700 (PDT) Received: from mail-wg0-f44.google.com (mail-wg0-f44.google.com [74.125.82.44]) by mx.google.com with ESMTPS id di1si855314wjc.44.2014.03.20.02.21.23 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:21:23 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.44 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=74.125.82.44; Received: by mail-wg0-f44.google.com with SMTP id m15so362045wgh.15 for ; Thu, 20 Mar 2014 02:21:23 -0700 (PDT) X-Received: by 10.180.207.10 with SMTP id ls10mr1809094wic.22.1395307283156; Thu, 20 Mar 2014 02:21:23 -0700 (PDT) Received: from lee--X1.home (host109-148-116-196.range109-148.btcentralplus.com. [109.148.116.196]) by mx.google.com with ESMTPSA id di9sm4735120wid.6.2014.03.20.02.21.21 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:21:22 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, computersforpeace@gmail.com Cc: linux-mtd@lists.infradead.org, dwmw2@infradead.org, Angus.Clark@st.com, Lee Jones Subject: [PATCH v6 03/36] mtd: st_spi_fsm: Initialise and configure the FSM for normal working conditions Date: Thu, 20 Mar 2014 09:20:35 +0000 Message-Id: <1395307268-12721-4-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> References: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch uses default values to initialise a connected flash chip. This includes; a device soft reset, setting of a safe working frequency, a switch into Fast Sequencing Mode, configuring of timing data and a purge of the FIFO. Acked-by Angus Clark Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 127 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 000bc25..7048ea7 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -74,6 +74,10 @@ #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16) #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24) +#define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA) +#define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0) +#define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00) + /* * Register: SPI_FAST_SEQ_TRANSFER_SIZE */ @@ -185,19 +189,136 @@ #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0) #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0) +#define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */ +#define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */ + +#define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */ + struct stfsm { struct device *dev; void __iomem *base; struct resource *region; struct mtd_info mtd; struct mutex lock; + + uint32_t fifo_dir_delay; }; +static inline uint32_t stfsm_fifo_available(struct stfsm *fsm) +{ + return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f; +} + +static void stfsm_clear_fifo(struct stfsm *fsm) +{ + uint32_t avail; + + for (;;) { + avail = stfsm_fifo_available(fsm); + if (!avail) + break; + + while (avail) { + readl(fsm->base + SPI_FAST_SEQ_DATA_REG); + avail--; + } + } +} + +static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode) +{ + int ret, timeout = 10; + + /* Wait for controller to accept mode change */ + while (--timeout) { + ret = readl(fsm->base + SPI_STA_MODE_CHANGE); + if (ret & 0x1) + break; + udelay(1); + } + + if (!timeout) + return -EBUSY; + + writel(mode, fsm->base + SPI_MODESELECT); + + return 0; +} + +static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq) +{ + uint32_t emi_freq; + uint32_t clk_div; + + /* TODO: Make this dynamic */ + emi_freq = STFSM_DEFAULT_EMI_FREQ; + + /* + * Calculate clk_div - values between 2 and 128 + * Multiple of 2, rounded up + */ + clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq); + if (clk_div < 2) + clk_div = 2; + else if (clk_div > 128) + clk_div = 128; + + /* + * Determine a suitable delay for the IP to complete a change of + * direction of the FIFO. The required delay is related to the clock + * divider used. The following heuristics are based on empirical tests, + * using a 100MHz EMI clock. + */ + if (clk_div <= 4) + fsm->fifo_dir_delay = 0; + else if (clk_div <= 10) + fsm->fifo_dir_delay = 1; + else + fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10); + + dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n", + emi_freq, spi_freq, clk_div); + + writel(clk_div, fsm->base + SPI_CLOCKDIV); +} + +static int stfsm_init(struct stfsm *fsm) +{ + int ret; + + /* Perform a soft reset of the FSM controller */ + writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG); + udelay(1); + writel(0, fsm->base + SPI_FAST_SEQ_CFG); + + /* Set clock to 'safe' frequency initially */ + stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ); + + /* Switch to FSM */ + ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM); + if (ret) + return ret; + + /* Set timing parameters */ + writel(SPI_CFG_DEVICE_ST | + SPI_CFG_DEFAULT_MIN_CS_HIGH | + SPI_CFG_DEFAULT_CS_SETUPHOLD | + SPI_CFG_DEFAULT_DATA_HOLD, + fsm->base + SPI_CONFIGDATA); + writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG); + + /* Clear FIFO, just in case */ + stfsm_clear_fifo(fsm); + + return 0; +} + static int stfsm_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct resource *res; struct stfsm *fsm; + int ret; if (!np) { dev_err(&pdev->dev, "No DT found\n"); @@ -227,6 +348,12 @@ static int stfsm_probe(struct platform_device *pdev) mutex_init(&fsm->lock); + ret = stfsm_init(fsm); + if (ret) { + dev_err(&pdev->dev, "Failed to initialise FSM Controller\n"); + return ret; + } + fsm->mtd.dev.parent = &pdev->dev; fsm->mtd.type = MTD_NORFLASH; fsm->mtd.writesize = 4;