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[2001:770:15f::2]) by mx.google.com with ESMTPS id hv2si5018350wjb.162.2014.04.01.06.51.38 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Apr 2014 06:51:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUz3W-0007LG-FG; Tue, 01 Apr 2014 13:48:47 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUz3I-0001tJ-R2; Tue, 01 Apr 2014 13:48:32 +0000 Received: from mail-wg0-f44.google.com ([74.125.82.44]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WUz2y-0001oW-Hj for linux-arm-kernel@lists.infradead.org; Tue, 01 Apr 2014 13:48:16 +0000 Received: by mail-wg0-f44.google.com with SMTP id m15so7517471wgh.27 for ; Tue, 01 Apr 2014 06:47:51 -0700 (PDT) X-Received: by 10.194.120.101 with SMTP id lb5mr4590581wjb.74.1396360071045; Tue, 01 Apr 2014 06:47:51 -0700 (PDT) Received: from ards-macbook-pro.local ([95.129.121.210]) by mx.google.com with ESMTPSA id 48sm40727180eee.2.2014.04.01.06.47.49 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Apr 2014 06:47:50 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, nico@linaro.org Subject: [PATCH v3 4/7] arm64/crypto: add shared macro to test for NEED_RESCHED Date: Tue, 1 Apr 2014 15:47:36 +0200 Message-Id: <1396360059-31949-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396360059-31949-1-git-send-email-ard.biesheuvel@linaro.org> References: <1396360059-31949-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140401_094812_754242_FF1B8913 X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.44 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This adds the asm macro definition 'b_if_no_resched' that performs a conditional branch depending on the preempt need_resched state. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/assembler.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index fd3e3924041b..296105fd3021 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -22,6 +22,11 @@ #include +#if defined(CONFIG_PREEMPT) || defined(CONFIG_PREEMPT_VOLUNTARY) +#include +#include +#endif + /* * Stack pushing/popping (register pairs only). Equivalent to store decrement * before, load increment after. @@ -146,3 +151,19 @@ lr .req x30 // link register #endif orr \rd, \lbits, \hbits, lsl #32 .endm + +/* + * Branch to 'lb' but only if we have not been tagged for preemption. + * + * Expects current->thread_info in ti, or NULL if running in interrupt + * context. reg is a scratch x register. + */ + .macro b_if_no_resched, ti, reg, lb +#if defined(CONFIG_PREEMPT) || defined(CONFIG_PREEMPT_VOLUNTARY) + cbz \ti, \lb /* have thread_info? */ + ldr \reg, [\ti, #TI_FLAGS] /* get flags */ + tbz \reg, #TIF_NEED_RESCHED, \lb /* need rescheduling? */ +#else + b \lb +#endif + .endm