From patchwork Tue Jun 10 18:51:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 31700 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f69.google.com (mail-qa0-f69.google.com [209.85.216.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4CAAE2100A for ; Tue, 10 Jun 2014 18:52:56 +0000 (UTC) Received: by mail-qa0-f69.google.com with SMTP id w8sf4147563qac.8 for ; Tue, 10 Jun 2014 11:52:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=US4TslEr1yNyKghC143yurTKcUBW7zSRhO0JZ0/qOpA=; b=fBD2gYGn2dmzi1/i45oxxdWegAxVJpddeeyaT8a4sPjbjFrHxITFL+eDzQhdcK0sJj tBhi9fe8T0ZyImQV/c0G/grkKvg1NJ7AR3nb7jIyjDCOvAHpqnBjhIhcozvWxUiSuUp0 KrqjsEMLCsHusGSLc5dU0ETSO2/Jivc44GCZWpgfY8hox0MLJOQvY4AkfD9kb8wvB9EY VeOoDYCfgZ2oY0+WusWWcnZsZCFoyEL0Lksqa245kQgGokeDXaO74SOxLvEf6rGMZDVT joiEsxHy/uO/tCZwBQzw5gPhWTuBARJtXOZGjHsBkO4zgWxESVh+oOIK6sNWmXIN4xs/ T+2g== X-Gm-Message-State: ALoCoQmMSX8Iu581ui4mWliT6E7ztzL3gideJPduYchzRv2V4Prr/8nVZa3dYagUPSbvcD0krA7/ X-Received: by 10.52.186.132 with SMTP id fk4mr4942265vdc.1.1402426376093; Tue, 10 Jun 2014 11:52:56 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.103.118 with SMTP id x109ls2223473qge.74.gmail; Tue, 10 Jun 2014 11:52:55 -0700 (PDT) X-Received: by 10.58.188.37 with SMTP id fx5mr35054549vec.17.1402426375755; Tue, 10 Jun 2014 11:52:55 -0700 (PDT) Received: from mail-vc0-f176.google.com (mail-vc0-f176.google.com [209.85.220.176]) by mx.google.com with ESMTPS id gu7si13373433vdc.22.2014.06.10.11.52.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 10 Jun 2014 11:52:55 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) client-ip=209.85.220.176; Received: by mail-vc0-f176.google.com with SMTP id ik5so737367vcb.35 for ; Tue, 10 Jun 2014 11:52:55 -0700 (PDT) X-Received: by 10.58.68.129 with SMTP id w1mr3751316vet.49.1402426375645; Tue, 10 Jun 2014 11:52:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.54.6 with SMTP id vs6csp247456vcb; Tue, 10 Jun 2014 11:52:55 -0700 (PDT) X-Received: by 10.66.141.76 with SMTP id rm12mr7604287pab.138.1402426374807; Tue, 10 Jun 2014 11:52:54 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id gu3si35211975pbb.232.2014.06.10.11.52.54; Tue, 10 Jun 2014 11:52:54 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752925AbaFJSwv (ORCPT + 27 others); Tue, 10 Jun 2014 14:52:51 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:56443 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752801AbaFJSwp (ORCPT ); Tue, 10 Jun 2014 14:52:45 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s5AIpMnm011303; Tue, 10 Jun 2014 13:51:22 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5AIpLqG014822; Tue, 10 Jun 2014 13:51:21 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Tue, 10 Jun 2014 13:51:21 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5AIpGKo012701; Tue, 10 Jun 2014 13:51:20 -0500 From: Murali Karicheri To: , , , , CC: Murali Karicheri , Santosh Shilimkar , Russell King , Grant Likely , Rob Herring , Mohit Kumar , Jingoo Han , Bjorn Helgaas , Pratyush Anand , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut , Arnd Bergmann , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap Subject: [PATCH v2 3/8] PCI: designware: update pcie core driver to work with dw hw version 3.65 Date: Tue, 10 Jun 2014 14:51:22 -0400 Message-ID: <1402426287-31157-4-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1402426287-31157-1-git-send-email-m-karicheri2@ti.com> References: <1402426287-31157-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , v3.65 version of the dw hw has MSI controller implemented in the application space. Add a version variable in the port struct to identify v3.65 hardware for different code treatment. This variable will have DW_V3_65 bit set when running on this hw version. The host init code is expected to set this version based on compatibility string dw,snps-pcie-v3.65. Some of the MSI specific functions from current DW driver are re-used on v3.65 hw. However on v3.65, MSI controller registers are in the application register space and PCIE_MSI_INTR0_ENABLE is not applicable. Modify assign_irq() to check for version and not execute the code for PCIE_MSI_INTR0_ENABLE configuration on v3.65 hw. Additionally MSI IRQ register in application space is written by EP to raise an MSI IRQ. So add a get_msi_data() function in pcie_host_ops to retrieve the register address in dw_msi_setup_irq(). v3.65 dw core driver implements this function. Also make some of the functions available in dw core driver global and make their prototypes available in the header file for re-use on v3.65. Signed-off-by: Murali Karicheri CC: Santosh Shilimkar CC: Russell King CC: Grant Likely CC: Rob Herring CC: Mohit Kumar CC: Jingoo Han CC: Bjorn Helgaas CC: Pratyush Anand CC: Richard Zhu CC: Kishon Vijay Abraham I CC: Marek Vasut CC: Arnd Bergmann CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: Randy Dunlap CC: Grant Likely --- drivers/pci/host/pcie-designware.c | 27 +++++++++++++++++---------- drivers/pci/host/pcie-designware.h | 16 ++++++++++++++++ 2 files changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index e4bd19a..f985811 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -277,11 +277,15 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) } set_bit(pos0 + i, pp->msi_irq_in_use); /*Enable corresponding interrupt in MSI interrupt controller */ - res = ((pos0 + i) / 32) * 12; - bit = (pos0 + i) % 32; - dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); - val |= 1 << bit; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); + if (!(pp->version & DW_V3_65)) { + res = ((pos0 + i) / 32) * 12; + bit = (pos0 + i) % 32; + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, + 4, &val); + val |= 1 << bit; + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, + 4, val); + } } *pos = pos0; @@ -349,7 +353,10 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, */ desc->msi_attrib.multiple = msgvec; - msg.address_lo = virt_to_phys((void *)pp->msi_data); + if (pp->ops->get_msi_data) + msg.address_lo = pp->ops->get_msi_data(pp); + else + msg.address_lo = virt_to_phys((void *)pp->msi_data); msg.address_hi = 0x0; msg.data = pos; write_msi_msg(irq, &msg); @@ -768,7 +775,7 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) +int dw_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; @@ -791,7 +798,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; struct pcie_port *pp = sys_to_pcie(sys); @@ -808,7 +815,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) return bus; } -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); int irq; @@ -820,7 +827,7 @@ static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static void dw_pcie_add_bus(struct pci_bus *bus) +void dw_pcie_add_bus(struct pci_bus *bus) { if (IS_ENABLED(CONFIG_PCI_MSI)) { struct pcie_port *pp = sys_to_pcie(bus->sysdata); diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 2d6dd66..3a6a6eb 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -39,6 +39,12 @@ struct pcie_port { void __iomem *va_cfg0_base; u64 cfg1_base; void __iomem *va_cfg1_base; + /* + * v3.65 DW hw implements application register space for + * MSI and has no ATU view port + */ +#define DW_V3_65 BIT(0) + u32 version; u64 io_base; u64 mem_base; spinlock_t conf_lock; @@ -68,6 +74,7 @@ struct pcie_host_ops { unsigned int devfn, int where, int size, u32 val); int (*link_up)(struct pcie_port *pp); void (*host_init)(struct pcie_port *pp); + u32 (*get_msi_data)(struct pcie_port *pp); }; int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); @@ -77,5 +84,14 @@ void dw_pcie_msi_init(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +int dw_pcie_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys); +void dw_pcie_add_bus(struct pci_bus *bus); +int dw_pcie_parse_resource(struct pcie_port *pp); +/* internal to DW common core driver */ +int dw_pcie_common_host_init(struct pcie_port *pp, struct hw_pci *hw); +int dw_pcie_msi_host_init(struct pcie_port *pp, struct device_node *np, + const struct irq_domain_ops *irq_ops); +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); #endif /* _PCIE_DESIGNWARE_H */