From patchwork Thu Jun 19 09:19:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 32168 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f200.google.com (mail-vc0-f200.google.com [209.85.220.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 7FC17206A0 for ; Thu, 19 Jun 2014 09:22:42 +0000 (UTC) Received: by mail-vc0-f200.google.com with SMTP id id10sf6102720vcb.7 for ; Thu, 19 Jun 2014 02:22:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:content-type:content-transfer-encoding; bh=ZVWsECO90RrPd0znLkVLFPDPOVQNdajUnNsadBWh+LE=; b=WTj2/o7Xy5DZbR5NWvHTgDkh/eBab6rJm16kQdUalnG7fzUSAdp/mrJzXcwn6e4lKp DPOhZYCpBxPk9Klsx8FpwqixP6iYZP0Mcu8gQ7IkkwyRa4RCBDAAdFDaMK79mIioPWal JQFr+Vtl8Ttd/Zm5fsorx7xjxsgMrNa3IrVPj3xR1NH4e6zMjV+XVThrTB3TMys8Ebh2 YH9lKwY0LP6lm4cxiIxbwj5xN6LGLoVYCKDrWYOVJWMnOP6VE4mdWLrQxn3+KvoLpb2C yyJ+6J2vY1DzbApi1EwYrWAf7pNJeLQxJdGCFyWhEK57k3M1U78/4Zxy06VNB4iNQ6HM AXEQ== X-Gm-Message-State: ALoCoQnys0QShjqpIFCw+ow33ioSJOshHNh0zddh4mI6c0dNpsM7jPygCvd6ckV7d4xOu0YM2SaB X-Received: by 10.236.47.163 with SMTP id t23mr1552036yhb.41.1403169762317; Thu, 19 Jun 2014 02:22:42 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.34.36 with SMTP id k33ls451456qgk.40.gmail; Thu, 19 Jun 2014 02:22:42 -0700 (PDT) X-Received: by 10.220.92.135 with SMTP id r7mr2999400vcm.11.1403169762236; Thu, 19 Jun 2014 02:22:42 -0700 (PDT) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id fh10si2096352vcb.48.2014.06.19.02.22.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 19 Jun 2014 02:22:42 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id hy10so1954120vcb.31 for ; Thu, 19 Jun 2014 02:22:42 -0700 (PDT) X-Received: by 10.58.8.12 with SMTP id n12mr3087032vea.28.1403169762147; Thu, 19 Jun 2014 02:22:42 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.54.6 with SMTP id vs6csp348270vcb; Thu, 19 Jun 2014 02:22:41 -0700 (PDT) X-Received: by 10.224.11.137 with SMTP id t9mr5295479qat.4.1403169761780; Thu, 19 Jun 2014 02:22:41 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id k3si5712345qas.117.2014.06.19.02.22.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jun 2014 02:22:41 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WxYVw-0000ax-Rq; Thu, 19 Jun 2014 09:20:12 +0000 Received: from fw-tnat.austin.arm.com ([217.140.110.23] helo=collaborate-mta1.arm.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WxYVt-0007xJ-19 for linux-arm-kernel@lists.infradead.org; Thu, 19 Jun 2014 09:20:09 +0000 Received: from e102391-lin.cambridge.arm.com (e102391-lin.cambridge.arm.com [10.1.209.143]) by collaborate-mta1.arm.com (Postfix) with ESMTP id 4BD3113FABF; Thu, 19 Jun 2014 04:19:50 -0500 (CDT) From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH v5 04/20] arm64: boot protocol documentation update for GICv3 Date: Thu, 19 Jun 2014 10:19:27 +0100 Message-Id: <1403169583-13668-5-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1403169583-13668-1-git-send-email-marc.zyngier@arm.com> References: <1403169583-13668-1-git-send-email-marc.zyngier@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140619_022009_162366_97DA095D X-CRM114-Status: UNSURE ( 9.73 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Catalin Marinas , Christoffer Dall X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: marc.zyngier@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Linux has some requirements that must be satisfied in order to boot on a system built with a GICv3. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- Documentation/arm64/booting.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 37fc4f6..e28ccec 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -141,6 +141,12 @@ Before jumping into the kernel, the following conditions must be met: the kernel image will be entered must be initialised by software at a higher exception level to prevent execution in an UNKNOWN state. + For systems with a GICv3 interrupt controller, it is expected that: + - If EL3 is present, it must program ICC_SRE_EL3.Enable (bit 3) to + 0b1 and ICC_SRE_EL3.SRE (bit 0) to 0b1. + - If the kernel is entered at EL1, EL2 must set ICC_SRE_EL2.Enable + (bit 3) to 0b1 and ICC_SRE_EL2.SRE (bit 0) to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level.