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[2001:1868:205::9]) by mx.google.com with ESMTPS id dy7si4774862pab.128.2014.07.09.23.57.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jul 2014 23:57:03 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58GV-0003EJ-6y; Thu, 10 Jul 2014 06:55:35 +0000 Received: from szxga03-in.huawei.com ([119.145.14.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58G6-0001ge-MD for linux-arm-kernel@lists.infradead.org; Thu, 10 Jul 2014 06:55:11 +0000 Received: from 172.24.2.119 (EHLO szxeml451-hub.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id ARL48867; Thu, 10 Jul 2014 14:54:22 +0800 (CST) Received: from localhost (10.177.27.142) by szxeml451-hub.china.huawei.com (10.82.67.194) with Microsoft SMTP Server id 14.3.158.1; Thu, 10 Jul 2014 14:54:13 +0800 From: Zhen Lei To: Catalin Marinas , Will Deacon , linux-arm-kernel Subject: [PATCH v3 01/13] iommu/arm: change some structure member types in arm_smmu_device Date: Thu, 10 Jul 2014 14:52:54 +0800 Message-ID: <1404975186-12032-2-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> References: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.27.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.53BE389F.00C2,ss=1,re=0.000,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2011-05-27 18:58:46 X-Mirapoint-Loop-Id: c0ac65ec11b08c9783dd9c0d04753ffe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140709_235511_118917_689331A7 X-CRM114-Status: GOOD ( 10.33 ) X-Spam-Score: -1.4 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [119.145.14.66 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [119.145.14.66 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Zhen Lei X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: thunder.leizhen@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Some structure members, such as s1_output_size, it's impossible large than 4G. Change unsigned long to u32 can save a few memory on ARM64. Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 1.8.0 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 1599354..d0f0021 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -352,8 +352,8 @@ struct arm_smmu_device { struct device_node *parent_of_node; void __iomem *base; - unsigned long size; - unsigned long pagesize; + u32 size; + u32 pagesize; #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) @@ -374,9 +374,9 @@ struct arm_smmu_device { u32 num_mapping_groups; DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); - unsigned long input_size; - unsigned long s1_output_size; - unsigned long s2_output_size; + u32 input_size; + u32 s1_output_size; + u32 s2_output_size; u32 num_global_irqs; u32 num_context_irqs; @@ -1676,7 +1676,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); } -static int arm_smmu_id_size_to_bits(int size) +static u32 arm_smmu_id_size_to_bits(u32 size) { switch (size) { case 0: @@ -1697,7 +1697,7 @@ static int arm_smmu_id_size_to_bits(int size) static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) { - unsigned long size; + u32 size; void __iomem *gr0_base = ARM_SMMU_GR0(smmu); u32 id; @@ -1782,8 +1782,8 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); size *= (smmu->pagesize << 1); if (smmu->size != size) - dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs " - "from mapped region size (0x%lx)!\n", size, smmu->size); + dev_warn(smmu->dev, "SMMU address space size (0x%x) differs " + "from mapped region size (0x%x)!\n", size, smmu->size); smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK; @@ -1804,21 +1804,21 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) * allocation (PTRS_PER_PGD). */ #ifdef CONFIG_64BIT - smmu->s1_output_size = min((unsigned long)VA_BITS, size); + smmu->s1_output_size = min((u32)VA_BITS, size); #else - smmu->s1_output_size = min(32UL, size); + smmu->s1_output_size = min(32U, size); #endif /* The stage-2 output mask is also applied for bypass */ size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); - smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size); + smmu->s2_output_size = min((u32)PHYS_MASK_SHIFT, size); if (smmu->version == 1) { smmu->input_size = 32; } else { #ifdef CONFIG_64BIT size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; - size = min(VA_BITS, arm_smmu_id_size_to_bits(size)); + size = min((u32)VA_BITS, arm_smmu_id_size_to_bits(size)); #else size = 32; #endif @@ -1834,7 +1834,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) } dev_notice(smmu->dev, - "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", + "\t%u-bit VA, %u-bit IPA, %u-bit PA\n", smmu->input_size, smmu->s1_output_size, smmu->s2_output_size); return 0; }