From patchwork Fri Jul 18 15:14:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 33874 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f71.google.com (mail-oa0-f71.google.com [209.85.219.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8A722208CF for ; Fri, 18 Jul 2014 15:17:17 +0000 (UTC) Received: by mail-oa0-f71.google.com with SMTP id g18sf15508631oah.6 for ; Fri, 18 Jul 2014 08:17:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=bIJZnnTo/JSmMayiWcidRBeMQDuLYQVnhKHZWprHH6A=; b=lnZK9/GxNnitw5f545Mf03fnW+vtcFn/ng8kUiL0cerzF/9w/OM58GjlUHWCvQEqnF q7dxBoTgfx1EVgTo2rrAmJEV1w4eWkpNQK1Z26vbhztYJ3aR6l0z43SYcxdoRhm8iPm/ jy9J+CKnva4wzI/ASmCu5rMdrELCKSryb2ZlX1woSec7JQ05PMcPo6MNOSvlP5HGLSB2 jMkVA1VutrnzJnXRkChj/QK5CFRyhy4shQhs7oBi+zx6FWAxON2McLoiOdzGfHDw3wqH yV9/1Vo1nQeJ8oplvNUkkLJNYsgzTm39ym+3hUyajj2wxH25oXX3GJdhv+G+iIL1COpK W76A== X-Gm-Message-State: ALoCoQl9mueRuHMh6reMeiKi7R2gwUr28Ip/a8kZXg2brDP6YP3dg9mspf2p08IIMaOtvkxV8Z6V X-Received: by 10.50.171.134 with SMTP id au6mr4868054igc.7.1405696636554; Fri, 18 Jul 2014 08:17:16 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.92.120 with SMTP id a111ls1001240qge.15.gmail; Fri, 18 Jul 2014 08:17:16 -0700 (PDT) X-Received: by 10.220.161.8 with SMTP id p8mr7010294vcx.4.1405696636344; Fri, 18 Jul 2014 08:17:16 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id ev7si6033792vdb.36.2014.07.18.08.17.15 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 18 Jul 2014 08:17:15 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id la4so7633246vcb.19 for ; Fri, 18 Jul 2014 08:17:14 -0700 (PDT) X-Received: by 10.53.5.230 with SMTP id cp6mr5464908vdd.25.1405696634776; Fri, 18 Jul 2014 08:17:14 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp19612vcb; Fri, 18 Jul 2014 08:17:03 -0700 (PDT) X-Received: by 10.66.142.135 with SMTP id rw7mr5979806pab.71.1405696576818; Fri, 18 Jul 2014 08:16:16 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bk6si3156440pdb.110.2014.07.18.08.16.07; Fri, 18 Jul 2014 08:16:07 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965615AbaGRPP7 (ORCPT + 24 others); Fri, 18 Jul 2014 11:15:59 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51665 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965092AbaGRPPz (ORCPT ); Fri, 18 Jul 2014 11:15:55 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6IFEWXT000512; Fri, 18 Jul 2014 10:14:32 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6IFEWRF030894; Fri, 18 Jul 2014 10:14:32 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 18 Jul 2014 10:14:32 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6IFESYm025193; Fri, 18 Jul 2014 10:14:31 -0500 From: Murali Karicheri To: , , CC: Murali Karicheri , Russell King , Grant Likely , Rob Herring , Bjorn Helgaas , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut , Arnd Bergmann , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap Subject: [PATCH v6 2/5] PCI: designware: refactor MSI code to work with v3.65 dw hardware Date: Fri, 18 Jul 2014 11:14:26 -0400 Message-ID: <1405696469-7172-3-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405696469-7172-1-git-send-email-m-karicheri2@ti.com> References: <1405696469-7172-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Keystone PCI controller is based on v3.65 version of the DW PCI h/w that implements MSI controller registers in application space compared to the newer version. This requires updates to the DW core API to support the PCI controller driver based on this old DW hardware. Add msi_irq_set()/clear() API functions to allow Set/Clear MSI IRQ enable bit in the application register. Also the old h/w uses MSI_IRQ register in application register space to raise MSI IRQ to the RC from EP. Current code uses the standard mechanism as per PCI spec. So add another API get_msi_data() to get the address of this register so that common code can be re-used on old h/w. Signed-off-by: Murali Karicheri Reviewed-by: Pratyush Anand Acked-by: Mohit Kumar Acked-by: Jingoo Han Acked-by: Santosh Shilimkar CC: Russell King CC: Grant Likely CC: Rob Herring CC: Bjorn Helgaas CC: Richard Zhu CC: Kishon Vijay Abraham I CC: Marek Vasut CC: Arnd Bergmann CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: Randy Dunlap CC: Grant Likely --- drivers/pci/host/pcie-designware.c | 50 ++++++++++++++++++++++++++---------- drivers/pci/host/pcie-designware.h | 3 +++ 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index d8f3af7..905941c 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -217,27 +217,47 @@ static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) return 0; } +static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) +{ + unsigned int res, bit, val; + + res = (irq / 32) * 12; + bit = irq % 32; + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); + val &= ~(1 << bit); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); +} + static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, unsigned int nvec, unsigned int pos) { - unsigned int i, res, bit, val; + unsigned int i; for (i = 0; i < nvec; i++) { irq_set_msi_desc_off(irq_base, i, NULL); clear_bit(pos + i, pp->msi_irq_in_use); /* Disable corresponding interrupt on MSI controller */ - res = ((pos + i) / 32) * 12; - bit = (pos + i) % 32; - dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); - val &= ~(1 << bit); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); + if (pp->ops->msi_clear_irq) + pp->ops->msi_clear_irq(pp, pos + i); + else + dw_pcie_msi_clear_irq(pp, pos + i); } } +static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) +{ + unsigned int res, bit, val; + + res = (irq / 32) * 12; + bit = irq % 32; + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); + val |= 1 << bit; + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); +} + static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) { - int res, bit, irq, pos0, pos1, i; - u32 val; + int irq, pos0, pos1, i; struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); if (!pp) { @@ -281,11 +301,10 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) } set_bit(pos0 + i, pp->msi_irq_in_use); /*Enable corresponding interrupt in MSI interrupt controller */ - res = ((pos0 + i) / 32) * 12; - bit = (pos0 + i) % 32; - dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); - val |= 1 << bit; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); + if (pp->ops->msi_set_irq) + pp->ops->msi_set_irq(pp, pos0 + i); + else + dw_pcie_msi_set_irq(pp, pos0 + i); } *pos = pos0; @@ -353,7 +372,10 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, */ desc->msi_attrib.multiple = msgvec; - msg.address_lo = virt_to_phys((void *)pp->msi_data); + if (pp->ops->get_msi_data) + msg.address_lo = pp->ops->get_msi_data(pp); + else + msg.address_lo = virt_to_phys((void *)pp->msi_data); msg.address_hi = 0x0; msg.data = pos; write_msi_msg(irq, &msg); diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 8121901..387f69e 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -67,6 +67,9 @@ struct pcie_host_ops { unsigned int devfn, int where, int size, u32 val); int (*link_up)(struct pcie_port *pp); void (*host_init)(struct pcie_port *pp); + void (*msi_set_irq)(struct pcie_port *pp, int irq); + void (*msi_clear_irq)(struct pcie_port *pp, int irq); + u32 (*get_msi_data)(struct pcie_port *pp); }; int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);