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[2001:1868:205::9]) by mx.google.com with ESMTPS id ky2si12989246pbc.9.2014.10.14.06.08.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Oct 2014 06:08:13 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe1o5-0003ni-Lb; Tue, 14 Oct 2014 13:06:29 +0000 Received: from mail-wi0-f182.google.com ([209.85.212.182]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe1mw-0002AD-4r for linux-arm-kernel@lists.infradead.org; Tue, 14 Oct 2014 13:05:18 +0000 Received: by mail-wi0-f182.google.com with SMTP id n3so10132958wiv.3 for ; Tue, 14 Oct 2014 06:04:54 -0700 (PDT) X-Received: by 10.180.96.226 with SMTP id dv2mr5188957wib.49.1413291893925; Tue, 14 Oct 2014 06:04:53 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id hg14sm170558wib.24.2014.10.14.06.04.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Oct 2014 06:04:53 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/8] ARM: realview: add PL022 SSP/SPI block to PB1176 DTS Date: Tue, 14 Oct 2014 15:04:12 +0200 Message-Id: <1413291855-499-5-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1413291855-499-1-git-send-email-linus.walleij@linaro.org> References: <1413291855-499-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141014_060518_376066_B63CA67B X-CRM114-Status: GOOD ( 11.13 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.182 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.182 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add the PL022 SSP/SPI block to the PL1176 DTS file, also define the separate SSPCLK clock derived from the 24MHz chrystal. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/arm-realview-pb1176.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 0e5b608ab9db..313a71756a18 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -56,6 +56,14 @@ clocks = <&xtal24mhz>; }; + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + uartclk: uartclk@24M { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -218,6 +226,15 @@ clock-names = "apb_pclk"; }; + pb1176_ssp: ssp@1010b000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1010b000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sspclk>, <&pclk>; + clock-names = "SSPCLK", "apb_pclk"; + }; + pb1176_serial0: serial@1010c000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1010c000 0x1000>;